18 resultados para High-throughput


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The aim of this work is to simulate and optically characterize the piezoelectric performance of complementary metal oxide semiconductor (CMOS) compatible microcantilevers based on aluminium nitride (AlN) and manufactured at room temperature. This study should facilitate the integration of piezoelectric micro-electro-mechanical systems (MEMS) such as microcantilevers, in CMOS technology. Besides compatibility with standard integrated circuit manufacturing procedures, low temperature processing also translates into higher throughput and, as a consequence, lower manufacturing costs. Thus, the use of the piezoelectric properties of AlN manufactured by reactive sputtering at room temperature is an important step towards the integration of this type of devices within future CMOS technology standards. To assess the reliability of our fabrication process, we have manufactured arrays of free-standing microcantilever beams of variable dimension and studied their piezoelectric performance. The characterization of the first out-of-plane modes of AlN-actuated piezoelectric microcantilevers has been carried out using two optical techniques: laser Doppler vibrometry (LDV) and white light interferometry (WLI). In order to actuate the cantilevers, a periodic chirp signal in certain frequency ranges was applied between the device electrodes. The nature of the different vibration modes detected has been studied and compared with that obtained by a finite element model based simulation (COMSOL Multiphysics), showing flexural as well as torsional modes. The correspondence between theoretical and experimental data is reasonably good, probing the viability of this high throughput and CMOS compatible fabrication process. To complete the study, X-ray diffraction as well as d33 piezoelectric coefficient measurements were also carried out.

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This paper presents a low-power, high-speed 4-data-path 128-point mixed-radix (radix-2 & radix-2 2 ) FFT processor for MB-OFDM Ultra-WideBand (UWB) systems. The processor employs the single-path delay feedback (SDF) pipelined structure for the proposed algorithm, it uses substructure-sharing multiplication units and shift-add structure other than traditional complex multipliers. Furthermore, the word lengths are properly chosen, thus the hardware costs and power consumption of the proposed FFT processor are efficiently reduced. The proposed FFT processor is verified and synthesized by using 0.13 µm CMOS technology with a supply voltage of 1.32 V. The implementation results indicate that the proposed 128-point mixed-radix FFT architecture supports a throughput rate of 1Gsample/s with lower power consumption in comparison to existing 128-point FFT architectures

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Quantum Key Distribution is carving its place among the tools used to secure communications. While a difficult technology, it enjoys benefits that set it apart from the rest, the most prominent is its provable security based on the laws of physics. QKD requires not only the mastering of signals at the quantum level, but also a classical processing to extract a secret-key from them. This postprocessing has been customarily studied in terms of the efficiency, a figure of merit that offers a biased view of the performance of real devices. Here we argue that it is the throughput the significant magnitude in practical QKD, specially in the case of high speed devices, where the differences are more marked, and give some examples contrasting the usual postprocessing schemes with new ones from modern coding theory. A good understanding of its implications is very important for the design of modern QKD devices.