A self-adaptive image processing application based on evolvable and scalable hardware

Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications.

A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

A scalable evolvable hardware processing array

Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits self-adaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case.

Desarrollo de un sistema hardware modular que implemente los instrumentos de un laboratorio de electr��nica

El poder disponer de la instrumentaci��n y los equipos electr��nicos resulta vital en el dise��o de circuitos anal��gicos. Permiten realizar las pruebas necesarias y el estudio para el buen funcionamiento de estos circuitos. Los equipos se pueden diferenciar en instrumentos de excitaci��n, los que proporcionan las se��ales al circuito, y en instrumentos de medida, los que miden las se��ales generadas por el circuito. Estos equipos sirven de gran ayuda pero a su vez tienen un precio elevado lo que impide en muchos casos disponer de ellos. Por esta principal desventaja, se hace necesario conseguir un dispositivo de bajo coste que sustituya de alguna manera a los equipos reales. Si el instrumento es de medida, este sistema de bajo coste puede ser implementado mediante un equipo hardware encargado de adquirir los datos y una aplicaci��n ejecut��ndose en un ordenador donde analizarlos y presentarlos en la pantalla. En el caso de que el instrumento sea de excitaci��n, el ��nico cometido del sistema hardware es el de proporcionar las se��ales cuya configuraci��n ha enviado el ordenador. En un equipo real, es el propio equipo el que debe realizar todas esas acciones: adquisici��n, procesamiento y presentaci��n de los datos. Adem��s, la dificultad de realizar modificaciones o ampliaciones de las funcionalidades en un instrumento tradicional con respecto a una aplicaci��n de queda patente. Debido a que un instrumento tradicional es un sistema cerrado y uno cuya configuraci��n o procesamiento de datos es hecho por una aplicaci��n, algunas de las modificaciones ser��an realizables modificando simplemente el software del programa de control, por lo que el coste de las modificaciones ser��a menor. En este proyecto se pretende implementar un sistema hardware que tenga las caracter��sticas y realice las funciones del equipamiento real que se pueda encontrar en un laboratorio de electr��nica. Tambi��n el desarrollo de una aplicaci��n encargada del control y el an��lisis de las se��ales adquiridas, cuya interfaz gr��fica se asemeje a la de los equipos reales para facilitar su uso. ABSTRACT. The instrumentation and electronic equipment are vital for the design of analogue circuits. They enable to perform the necessary testing and study for the proper functioning of these circuits. The devices can be classified into the following categories: excitation instruments, which transmit the signals to the circuit, and measuring instruments, those in charge of measuring the signals produced by the circuit. This equipment is considerably helpful, however, its high price often makes it hardly accessible. For this reason, low price equipment is needed in order to replace real devices. If the instrument is measuring, this low cost system can be implemented by hardware equipment to acquire the data and running on a computer where analyzing and present on the screen application. In case of an excitation the instrument, the only task of the hardware system is to provide signals which sent the computer configuration. In a real instrument, is the instrument itself that must perform all these actions: acquisition, processing and presentation of data. Moreover, the difficulty of making changes or additions to the features in traditional devices with respect to an application running on a computer is evident. This is due to the fact that a traditional instrument is a closed system and its configuration or data processing is made by an application. Therefore, certain changes can be made just by modifying the control program software. Consequently, the cost of these modifications is lower. This project aims to implement a hardware system with the same features and functions of any real device, available in an electronics laboratory. Besides, it aims to develop an application for the monitoring and analysis of acquired signals. This application is provided with a graphic interface resembling those of real devices in order to facilitate its use.

Hardware timestamping for image acquisition system based on FlexRIO and IEEE 1588 v2 Standard

Current fusion devices consist of multiple diagnostics and hundreds or even thousands of signals. This situation forces on multiple occasions to use distributed data acquisition systems as the best approach. In this type of distributed systems, one of the most important issues is the synchronization between signals, so that it is possible to have a temporal correlation as accurate as possible between the acquired samples of all channels. In last decades, many fusion devices use different types of video cameras to provide inside views of the vessel during operations and to monitor plasma behavior. The synchronization between each video frame and the rest of the different signals acquired from any other diagnostics is essential in order to know correctly the plasma evolution, since it is possible to analyze jointly all the information having accurate knowledge of their temporal correlation. The developed system described in this paper allows timestamping image frames in a real-time acquisition and processing system using 1588 clock distribution. The system has been implemented using FPGA based devices together with a 1588 synchronized timing card (see Fig.1). The solution is based on a previous system [1] that allows image acquisition and real-time image processing based on PXIe technology. This architecture is fully compatible with the ITER Fast Controllers [2] and offers integration with EPICS to control and monitor the entire system. However, this set-up is not able to timestamp the frames acquired since the frame grabber module does not present any type of timing input (IRIG-B, GPS, PTP). To solve this lack, an IEEE1588 PXI timing device its used to provide an accurate way to synchronize distributed data acquisition systems using the Precision Time Protocol (PTP) IEEE 1588 2008 standard. This local timing device can be connected to a master clock device for global synchronization. The timing device has a buffer timestamp for each PXI trigger line and requires tha- a software application assigns each frame the corresponding timestamp. The previous action is critical and cannot be achieved if the frame rate is high. To solve this problem, it has been designed a solution that distributes the clock from the IEEE 1588 timing card to all FlexRIO devices [3]. This solution uses two PXI trigger lines that provide the capacity to assign timestamps to every frame acquired and register events by hardware in a deterministic way. The system provides a solution for timestamping frames to synchronize them with the rest of the different signals.

Elementos de sistemas operativos, de representaci��n de la informaci��n y de procesadores hardware y software

Conceptos de representaci��n binaria y de arquitecturas hardware y software con pr��cticas de laboratorio sobre Linux y ejercicios resueltos.

A proposal for an Internet of Things-based monitoring system composed by low capability, open source and open hardware devices

The Internet of Things makes use of a huge disparity of technologies at very different levels that help one to the other to accomplish goals that were previously regarded as unthinkable in terms of ubiquity or scalability. If the Internet of Things is expected to interconnect every day devices or appliances and enable communications between them, a broad range of new services, applications and products can be foreseen. For example, monitoring is a process where sensors have widespread use for measuring environmental parameters (temperature, light, chemical agents, etc.) but obtaining readings at the exact physical point they want to be obtained from, or about the exact wanted parameter can be a clumsy, time-consuming task that is not easily adaptable to new requirements. In order to tackle this challenge, a proposal on a system used to monitor any conceivable environment, which additionally is able to monitor the status of its own components and heal some of the most usual issues of a Wireless Sensor Network, is presented here in detail, covering all the layers that give it shape in terms of devices, communications or services.

Collaborative Evolution Strategies on Evolvable Hardware Networked Elements

Dynamic and Partial Reconfiguration allows systems to change some parts of their hardware at run time. This feature favours the inclusion of evolutionary strategies to provide optimised solutions to the same problem so that they can be mixed and compared in a way that only the best ones prevail. At the same time, distributed intelligence permits systems to work in a collaborative way to jointly improve their global capabilities. This work presents a combination of both approaches where hardware evolution is performed both at local and network level in order to improve an image filter application in terms of performance, robustness and providing the capacity of avoiding local minimums, which is the main drawback of some evolutionary approaches.

Development of Brain-Computer Interfaces using Evolvable Hardware

Brain-Computer Interfaces are usually tackled from a medical point of view, correlating observed phenomena to physical facts known about the brain. Existing methods of classification lie in the application of deterministic algorithms and depend on certain degree of knowledge about the underlying phenomena so as to process data. In this demo, different architectures for an evolvable hardware classifier implemented on an FPGA are proposed, in line with the objective of generalizing evolutionary algorithms regardless of the application.

Power-Aware Multi-Objective Evolvable Hardware System on an FPGA

Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The objective of the evolution may not be a single one; in this work, power consumption is taken into consideration, together with the quality of filtering, as the measure of performance, of a noisy image. Pareto optimality is applied to the evolutionary process, in order to find a representative set of optimal solutions as for performance and power consumption. The main contributions of this paper are: implementing an evolvable system on a low-power Spartan-6 FPGA included in a Wireless Sensor Network node and, by enabling the availability of a real measure of power consumption at run-time, achieving the capability of multi-objective evolution, that yields different optimal configurations, among which the selected one will depend on the relative ���weights��� of performance and power consumption.

Algorithms hardware implementation for ultrasonic data processing in SHM system

Nowadays, devices that monitor the health of structures consume a lot of power and need a lot of time to acquire, process, and send the information about the structure to the main processing unit. To decrease this time, fast electronic devices are starting to be used to accelerate this processing. In this paper some hardware algorithms implemented in an electronic logic programming device are described. The goal of this implementation is accelerate the process and diminish the information that has to be send. By reaching this goal, the time the processor needs for treating all the information is reduced and so the power consumption is reduced too.

Distribution of microservices for hardware interoperability in the Smart Grid

Due to the significant increase of population and their natural desire of improving their standard of living, usage of energy extracted from world commodities, especially shaped as electricity, has increased in an intense manner during the last decades. This fact brings up a challenge with a complicated solution, which is how to guarantee that there will be enough energy so as to satisfy the energy demand of the world population. Among all the possible solutions that can be adopted to mitigate this problem one of them is almost of mandatory adoption, which consists of rationalizing energy utilization, in a way that its wasteful usage is minimized and it can be leveraged during a longer period of time. One of the ways to achieve it is by means of the improvement of the power distribution grid, so that it will be able to react in a more efficient manner against common issues, such as energy demand peaks or inaccurate electricity consumption forecasts. However, in order to be able to implement this improvement it is necessary to use technologies from the ICT (Information and Communication Technologies) sphere that often present challenges in some key areas: advanced metering infrastructure integration, interoperability and interconnectivity of the devices, interfaces to offer the applications, security measures design, etc. All these challenges may imply slowing down the adoption of the smart grid as a system to prolong the lifespan and utilization of the available energy. A proposal for an intermediation architecture that will make possible solving these challenges is put forward in this Master Thesis. Besides, one implementation and the tests that have been carried out to know the performance of the presented concepts have been included as well, in a way that it can be proved that the challenges set out by the smart grid can be resolved. RESUMEN. Debido al incremento significativo de la poblaci��n y su deseo natural de mejorar su nivel de vida, la utilizaci��n de la energ��a extra��da de las materias primas mundiales, especialmente en forma de electricidad, ha aumentado de manera intensa durante las ��ltimas d��cadas. Este hecho plantea un reto de soluci��n complicada, el cual es c��mo garantizar que se dispondr�� de la energ��a suficiente como para satisfacer la demanda energ��tica de la poblaci��n mundial. De entre todas las soluciones posibles que se pueden adoptar para mitigar este problema una de ellas es de casi obligatoria adopci��n, la cual consiste en racionalizar la utilizaci��n de la energ��a, de tal forma que se minimice su malgasto y pueda aprovecharse durante m��s tiempo. Una de las maneras de conseguirlo es mediante la mejora de la red de distribuci��n de electricidad para que ��sta pueda reaccionar de manera m��s eficaz contra problemas comunes, tales como los picos de demanda de energ��a o previsiones imprecisas acerca del consumo de electricidad. Sin embargo, para poder implementar esta mejora es necesario utilizar tecnolog��as del ��mbito de las TIC (Tecnolog��as de la Informaci��n y la Comunicaci��n) que a menudo presentan problemas en algunas ��reas clave: integraci��n de infraestructura de medici��n avanzada, interoperabilidad e interconectividad de los dispositivos, interfaces que ofrecer a las aplicaciones, dise��o de medidas de seguridad, etc. Todos estos retos pueden implicar una ralentizaci��n en la adopci��n de la red el��ctrica inteligente como un sistema para alargar la vida y la utilizaci��n de la energ��a disponible. En este Trabajo Fin de M��ster se sugiere una propuesta para una arquitectura de intermediaci��n que posibilite la resoluci��n de estos retos. Adem��s, una implementaci��n y las pruebas que se han llevado a cabo para conocer el rendimiento de los conceptos presentados tambi��n han sido incluidas, de tal forma que se demuestre que los retos que plantea la red el��ctrica inteligente pueden ser solventados.

Parametric and structural self-adaptation of embedded systems using evolvable hardware

Los sistemas empotrados han sido concebidos tradicionalmente como sistemas de procesamiento espec��ficos que realizan una tarea fija durante toda su vida ��til. Para cumplir con requisitos estrictos de coste, tama��o y peso, el equipo de dise��o debe optimizar su funcionamiento para condiciones muy espec��ficas. Sin embargo, la demanda de mayor versatilidad, un funcionamiento m��s inteligente y, en definitiva, una mayor capacidad de procesamiento comenzaron a chocar con estas limitaciones, agravado por la incertidumbre asociada a entornos de operaci��n cada vez m��s din��micos donde comenzaban a ser desplegados progresivamente. Esto trajo como resultado una necesidad creciente de que los sistemas pudieran responder por si solos a eventos inesperados en tiempo dise��o tales como: cambios en las caracter��sticas de los datos de entrada y el entorno del sistema en general; cambios en la propia plataforma de c��mputo, por ejemplo debido a fallos o defectos de fabricaci��n; y cambios en las propias especificaciones funcionales causados por unos objetivos del sistema din��micos y cambiantes. Como consecuencia, la complejidad del sistema aumenta, pero a cambio se habilita progresivamente una capacidad de adaptaci��n aut��noma sin intervenci��n humana a lo largo de la vida ��til, permitiendo que tomen sus propias decisiones en tiempo de ejecuci��n. ��stos sistemas se conocen, en general, como sistemas auto-adaptativos y tienen, entre otras caracter��sticas, las de auto-configuraci��n, auto-optimizaci��n y auto-reparaci��n. T��picamente, la parte soft de un sistema es mayoritariamente la ��nica utilizada para proporcionar algunas capacidades de adaptaci��n a un sistema. Sin embargo, la proporci��n rendimiento/potencia en dispositivos software como microprocesadores en muchas ocasiones no es adecuada para sistemas empotrados. En este escenario, el aumento resultante en la complejidad de las aplicaciones est�� siendo abordado parcialmente mediante un aumento en la complejidad de los dispositivos en forma de multi/many-cores; pero desafortunadamente, esto hace que el consumo de potencia tambi��n aumente. Adem��s, la mejora en metodolog��as de dise��o no ha sido acorde como para poder utilizar toda la capacidad de c��mputo disponible proporcionada por los n��cleos. Por todo ello, no se est��n satisfaciendo adecuadamente las demandas de c��mputo que imponen las nuevas aplicaciones. La soluci��n tradicional para mejorar la proporci��n rendimiento/potencia ha sido el cambio a unas especificaciones hardware, principalmente usando ASICs. Sin embargo, los costes de un ASIC son altamente prohibitivos excepto en algunos casos de producci��n en masa y adem��s la naturaleza est��tica de su estructura complica la soluci��n a las necesidades de adaptaci��n. Los avances en tecnolog��as de fabricaci��n han hecho que la FPGA, una vez lenta y peque��a, usada como glue logic en sistemas mayores, haya crecido hasta convertirse en un dispositivo de c��mputo reconfigurable de gran potencia, con una cantidad enorme de recursos l��gicos computacionales y cores hardware empotrados de procesamiento de se��al y de prop��sito general. Sus capacidades de reconfiguraci��n han permitido combinar la flexibilidad propia del software con el rendimiento del procesamiento en hardware, lo que tiene la potencialidad de provocar un cambio de paradigma en arquitectura de computadores, pues el hardware no puede ya ser considerado m��s como est��tico. El motivo es que como en el caso de las FPGAs basadas en tecnolog��a SRAM, la reconfiguraci��n parcial din��mica (DPR, Dynamic Partial Reconfiguration) es posible. Esto significa que se puede modificar (reconfigurar) un subconjunto de los recursos computacionales en tiempo de ejecuci��n mientras el resto permanecen activos. Adem��s, este proceso de reconfiguraci��n puede ser ejecutado internamente por el propio dispositivo. El avance tecnol��gico en dispositivos hardware reconfigurables se encuentra recogido bajo el campo conocido como Computaci��n Reconfigurable (RC, Reconfigurable Computing). Uno de los campos de aplicaci��n m��s ex��ticos y menos convencionales que ha posibilitado la computaci��n reconfigurable es el conocido como Hardware Evolutivo (EHW, Evolvable Hardware), en el cual se encuentra enmarcada esta tesis. La idea principal del concepto consiste en convertir hardware que es adaptable a trav��s de reconfiguraci��n en una entidad evolutiva sujeta a las fuerzas de un proceso evolutivo inspirado en el de las especies biol��gicas naturales, que gu��a la direcci��n del cambio. Es una aplicaci��n m��s del campo de la Computaci��n Evolutiva (EC, Evolutionary Computation), que comprende una serie de algoritmos de optimizaci��n global conocidos como Algoritmos Evolutivos (EA, Evolutionary Algorithms), y que son considerados como algoritmos universales de resoluci��n de problemas. En analog��a al proceso biol��gico de la evoluci��n, en el hardware evolutivo el sujeto de la evoluci��n es una poblaci��n de circuitos que intenta adaptarse a su entorno mediante una adecuaci��n progresiva generaci��n tras generaci��n. Los individuos pasan a ser configuraciones de circuitos en forma de bitstreams caracterizados por descripciones de circuitos reconfigurables. Seleccionando aquellos que se comportan mejor, es decir, que tienen una mejor adecuaci��n (o fitness) despu��s de ser evaluados, y us��ndolos como padres de la siguiente generaci��n, el algoritmo evolutivo crea una nueva poblaci��n hija usando operadores gen��ticos como la mutaci��n y la recombinaci��n. Seg��n se van sucediendo generaciones, se espera que la poblaci��n en conjunto se aproxime a la soluci��n ��ptima al problema de encontrar una configuraci��n del circuito adecuada que satisfaga las especificaciones. El estado de la tecnolog��a de reconfiguraci��n despu��s de que la familia de FPGAs XC6200 de Xilinx fuera retirada y reemplazada por las familias Virtex a finales de los 90, supuso un gran obst��culo para el avance en hardware evolutivo; formatos de bitstream cerrados (no conocidos p��blicamente); dependencia de herramientas del fabricante con soporte limitado de DPR; una velocidad de reconfiguraci��n lenta; y el hecho de que modificaciones aleatorias del bitstream pudieran resultar peligrosas para la integridad del dispositivo, son algunas de estas razones. Sin embargo, una propuesta a principios de los a��os 2000 permiti�� mantener la investigaci��n en el campo mientras la tecnolog��a de DPR continuaba madurando, el Circuito Virtual Reconfigurable (VRC, Virtual Reconfigurable Circuit). En esencia, un VRC en una FPGA es una capa virtual que act��a como un circuito reconfigurable de aplicaci��n espec��fica sobre la estructura nativa de la FPGA que reduce la complejidad del proceso reconfiguraci��n y aumenta su velocidad (comparada con la reconfiguraci��n nativa). Es un array de nodos computacionales especificados usando descripciones HDL est��ndar que define recursos reconfigurables ad-hoc: multiplexores de rutado y un conjunto de elementos de procesamiento configurables, cada uno de los cuales tiene implementadas todas las funciones requeridas, que pueden seleccionarse a trav��s de multiplexores tal y como ocurre en una ALU de un microprocesador. Un registro grande act��a como memoria de configuraci��n, por lo que la reconfiguraci��n del VRC es muy r��pida ya que tan s��lo implica la escritura de este registro, el cual controla las se��ales de selecci��n del conjunto de multiplexores. Sin embargo, esta capa virtual provoca: un incremento de ��rea debido a la implementaci��n simult��nea de cada funci��n en cada nodo del array m��s los multiplexores y un aumento del retardo debido a los multiplexores, reduciendo la frecuencia de funcionamiento m��xima. La naturaleza del hardware evolutivo, capaz de optimizar su propio comportamiento computacional, le convierten en un buen candidato para avanzar en la investigaci��n sobre sistemas auto-adaptativos. Combinar un sustrato de c��mputo auto-reconfigurable capaz de ser modificado din��micamente en tiempo de ejecuci��n con un algoritmo empotrado que proporcione una direcci��n de cambio, puede ayudar a satisfacer los requisitos de adaptaci��n aut��noma de sistemas empotrados basados en FPGA. La propuesta principal de esta tesis est�� por tanto dirigida a contribuir a la auto-adaptaci��n del hardware de procesamiento de sistemas empotrados basados en FPGA mediante hardware evolutivo. Esto se ha abordado considerando que el comportamiento computacional de un sistema puede ser modificado cambiando cualquiera de sus dos partes constitutivas: una estructura hard subyacente y un conjunto de par��metros soft. De esta distinci��n, se derivan dos lineas de trabajo. Por un lado, auto-adaptaci��n param��trica, y por otro auto-adaptaci��n estructural. El objetivo perseguido en el caso de la auto-adaptaci��n param��trica es la implementaci��n de t��cnicas de optimizaci��n evolutiva complejas en sistemas empotrados con recursos limitados para la adaptaci��n param��trica online de circuitos de procesamiento de se��al. La aplicaci��n seleccionada como prueba de concepto es la optimizaci��n para tipos muy espec��ficos de im��genes de los coeficientes de los filtros de transformadas wavelet discretas (DWT, DiscreteWavelet Transform), orientada a la compresi��n de im��genes. Por tanto, el objetivo requerido de la evoluci��n es una compresi��n adaptativa y m��s eficiente comparada con los procedimientos est��ndar. El principal reto radica en reducir la necesidad de recursos de supercomputaci��n para el proceso de optimizaci��n propuesto en trabajos previos, de modo que se adec��e para la ejecuci��n en sistemas empotrados. En cuanto a la auto-adaptaci��n estructural, el objetivo de la tesis es la implementaci��n de circuitos auto-adaptativos en sistemas evolutivos basados en FPGA mediante un uso eficiente de sus capacidades de reconfiguraci��n nativas. En este caso, la prueba de concepto es la evoluci��n de tareas de procesamiento de imagen tales como el filtrado de tipos desconocidos y cambiantes de ruido y la detecci��n de bordes en la imagen. En general, el objetivo es la evoluci��n en tiempo de ejecuci��n de tareas de procesamiento de imagen desconocidas en tiempo de dise��o (dentro de un cierto grado de complejidad). En este caso, el objetivo de la propuesta es la incorporaci��n de DPR en EHW para evolucionar la arquitectura de un array sist��lico adaptable mediante reconfiguraci��n cuya capacidad de evoluci��n no hab��a sido estudiada previamente. Para conseguir los dos objetivos mencionados, esta tesis propone originalmente una plataforma evolutiva que integra un motor de adaptaci��n (AE, Adaptation Engine), un motor de reconfiguraci��n (RE, Reconfiguration Engine) y un motor computacional (CE, Computing Engine) adaptable. El el caso de adaptaci��n param��trica, la plataforma propuesta est�� caracterizada por: ��� un CE caracterizado por un n��cleo de procesamiento hardware de DWT adaptable mediante registros reconfigurables que contienen los coeficientes de los filtros wavelet ��� un algoritmo evolutivo como AE que busca filtros wavelet candidatos a trav��s de un proceso de optimizaci��n param��trica desarrollado espec��ficamente para sistemas caracterizados por recursos de procesamiento limitados ��� un nuevo operador de mutaci��n simplificado para el algoritmo evolutivo utilizado, que junto con un mecanismo de evaluaci��n r��pida de filtros wavelet candidatos derivado de la literatura actual, asegura la viabilidad de la b��squeda evolutiva asociada a la adaptaci��n de wavelets. En el caso de adaptaci��n estructural, la plataforma propuesta toma la forma de: ��� un CE basado en una plantilla de array sist��lico reconfigurable de 2 dimensiones compuesto de nodos de procesamiento reconfigurables ��� un algoritmo evolutivo como AE que busca configuraciones candidatas del array usando un conjunto de funcionalidades de procesamiento para los nodos disponible en una biblioteca accesible en tiempo de ejecuci��n ��� un RE hardware que explota la capacidad de reconfiguraci��n nativa de las FPGAs haciendo un uso eficiente de los recursos reconfigurables del dispositivo para cambiar el comportamiento del CE en tiempo de ejecuci��n ��� una biblioteca de elementos de procesamiento reconfigurables caracterizada por bitstreams parciales independientes de la posici��n, usados como el conjunto de configuraciones disponibles para los nodos de procesamiento del array Las contribuciones principales de esta tesis se pueden resumir en la siguiente lista: ��� Una plataforma evolutiva basada en FPGA para la auto-adaptaci��n param��trica y estructural de sistemas empotrados compuesta por un motor computacional (CE), un motor de adaptaci��n (AE) evolutivo y un motor de reconfiguraci��n (RE). Esta plataforma se ha desarrollado y particularizado para los casos de auto-adaptaci��n param��trica y estructural. ��� En cuanto a la auto-adaptaci��n param��trica, las contribuciones principales son: ��� Un motor computacional adaptable mediante registros que permite la adaptaci��n param��trica de los coeficientes de una implementaci��n hardware adaptativa de un n��cleo de DWT. ��� Un motor de adaptaci��n basado en un algoritmo evolutivo desarrollado espec��ficamente para optimizaci��n num��rica, aplicada a los coeficientes de filtros wavelet en sistemas empotrados con recursos limitados. ��� Un n��cleo IP de DWT auto-adaptativo en tiempo de ejecuci��n para sistemas empotrados que permite la optimizaci��n online del rendimiento de la transformada para compresi��n de im��genes en entornos espec��ficos de despliegue, caracterizados por tipos diferentes de se��al de entrada. ��� Un modelo software y una implementaci��n hardware de una herramienta para la construcci��n evolutiva autom��tica de transformadas wavelet espec��ficas. ��� Por ��ltimo, en cuanto a la auto-adaptaci��n estructural, las contribuciones principales son: ��� Un motor computacional adaptable mediante reconfiguraci��n nativa de FPGAs caracterizado por una plantilla de array sist��lico en dos dimensiones de nodos de procesamiento reconfigurables. Es posible mapear diferentes tareas de c��mputo en el array usando una biblioteca de elementos sencillos de procesamiento reconfigurables. ��� Definici��n de una biblioteca de elementos de procesamiento apropiada para la s��ntesis aut��noma en tiempo de ejecuci��n de diferentes tareas de procesamiento de imagen. ��� Incorporaci��n eficiente de la reconfiguraci��n parcial din��mica (DPR) en sistemas de hardware evolutivo, superando los principales inconvenientes de propuestas previas como los circuitos reconfigurables virtuales (VRCs). En este trabajo tambi��n se comparan originalmente los detalles de implementaci��n de ambas propuestas. ��� Una plataforma tolerante a fallos, auto-curativa, que permite la recuperaci��n funcional online en entornos peligrosos. La plataforma ha sido caracterizada desde una perspectiva de tolerancia a fallos: se proponen modelos de fallo a nivel de CLB y de elemento de procesamiento, y usando el motor de reconfiguraci��n, se hace un an��lisis sistem��tico de fallos para un fallo en cada elemento de procesamiento y para dos fallos acumulados. ��� Una plataforma con calidad de filtrado din��mica que permite la adaptaci��n online a tipos de ruido diferentes y diferentes comportamientos computacionales teniendo en cuenta los recursos de procesamiento disponibles. Por un lado, se evolucionan filtros con comportamientos no destructivos, que permiten esquemas de filtrado en cascada escalables; y por otro, tambi��n se evolucionan filtros escalables teniendo en cuenta requisitos computacionales de filtrado cambiantes din��micamente. Este documento est�� organizado en cuatro partes y nueve cap��tulos. La primera parte contiene el cap��tulo 1, una introducci��n y motivaci��n sobre este trabajo de tesis. A continuaci��n, el marco de referencia en el que se enmarca esta tesis se analiza en la segunda parte: el cap��tulo 2 contiene una introducci��n a los conceptos de auto-adaptaci��n y computaci��n auton��mica (autonomic computing) como un campo de investigaci��n m��s general que el muy espec��fico de este trabajo; el cap��tulo 3 introduce la computaci��n evolutiva como la t��cnica para dirigir la adaptaci��n; el cap��tulo 4 analiza las plataformas de computaci��n reconfigurables como la tecnolog��a para albergar hardware auto-adaptativo; y finalmente, el cap��tulo 5 define, clasifica y hace un sondeo del campo del hardware evolutivo. Seguidamente, la tercera parte de este trabajo contiene la propuesta, desarrollo y resultados obtenidos: mientras que el cap��tulo 6 contiene una declaraci��n de los objetivos de la tesis y la descripci��n de la propuesta en su conjunto, los cap��tulos 7 y 8 abordan la auto-adaptaci��n param��trica y estructural, respectivamente. Finalmente, el cap��tulo 9 de la parte 4 concluye el trabajo y describe caminos de investigaci��n futuros. ABSTRACT Embedded systems have traditionally been conceived to be specific-purpose computers with one, fixed computational task for their whole lifetime. Stringent requirements in terms of cost, size and weight forced designers to highly optimise their operation for very specific conditions. However, demands for versatility, more intelligent behaviour and, in summary, an increased computing capability began to clash with these limitations, intensified by the uncertainty associated to the more dynamic operating environments where they were progressively being deployed. This brought as a result an increasing need for systems to respond by themselves to unexpected events at design time, such as: changes in input data characteristics and system environment in general; changes in the computing platform itself, e.g., due to faults and fabrication defects; and changes in functional specifications caused by dynamically changing system objectives. As a consequence, systems complexity is increasing, but in turn, autonomous lifetime adaptation without human intervention is being progressively enabled, allowing them to take their own decisions at run-time. This type of systems is known, in general, as selfadaptive, and are able, among others, of self-configuration, self-optimisation and self-repair. Traditionally, the soft part of a system has mostly been so far the only place to provide systems with some degree of adaptation capabilities. However, the performance to power ratios of software driven devices like microprocessors are not adequate for embedded systems in many situations. In this scenario, the resulting rise in applications complexity is being partly addressed by rising devices complexity in the form of multi and many core devices; but sadly, this keeps on increasing power consumption. Besides, design methodologies have not been improved accordingly to completely leverage the available computational power from all these cores. Altogether, these factors make that the computing demands new applications pose are not being wholly satisfied. The traditional solution to improve performance to power ratios has been the switch to hardware driven specifications, mainly using ASICs. However, their costs are highly prohibitive except for some mass production cases and besidesthe static nature of its structure complicates the solution to the adaptation needs. The advancements in fabrication technologies have made that the once slow, small FPGA used as glue logic in bigger systems, had grown to be a very powerful, reconfigurable computing device with a vast amount of computational logic resources and embedded, hardened signal and general purpose processing cores. Its reconfiguration capabilities have enabled software-like flexibility to be combined with hardware-like computing performance, which has the potential to cause a paradigm shift in computer architecture since hardware cannot be considered as static anymore. This is so, since, as is the case with SRAMbased FPGAs, Dynamic Partial Reconfiguration (DPR) is possible. This means that subsets of the FPGA computational resources can now be changed (reconfigured) at run-time while the rest remains active. Besides, this reconfiguration process can be triggered internally by the device itself. This technological boost in reconfigurable hardware devices is actually covered under the field known as Reconfigurable Computing. One of the most exotic fields of application that Reconfigurable Computing has enabled is the known as Evolvable Hardware (EHW), in which this dissertation is framed. The main idea behind the concept is turning hardware that is adaptable through reconfiguration into an evolvable entity subject to the forces of an evolutionary process, inspired by that of natural, biological species, that guides the direction of change. It is yet another application of the field of Evolutionary Computation (EC), which comprises a set of global optimisation algorithms known as Evolutionary Algorithms (EAs), considered as universal problem solvers. In analogy to the biological process of evolution, in EHW the subject of evolution is a population of circuits that tries to get adapted to its surrounding environment by progressively getting better fitted to it generation after generation. Individuals become circuit configurations representing bitstreams that feature reconfigurable circuit descriptions. By selecting those that behave better, i.e., with a higher fitness value after being evaluated, and using them as parents of the following generation, the EA creates a new offspring population by using so called genetic operators like mutation and recombination. As generations succeed one another, the whole population is expected to approach to the optimum solution to the problem of finding an adequate circuit configuration that fulfils system objectives. The state of reconfiguration technology after Xilinx XC6200 FPGA family was discontinued and replaced by Virtex families in the late 90s, was a major obstacle for advancements in EHW; closed (non publicly known) bitstream formats; dependence on manufacturer tools with highly limiting support of DPR; slow speed of reconfiguration; and random bitstream modifications being potentially hazardous for device integrity, are some of these reasons. However, a proposal in the first 2000s allowed to keep investigating in this field while DPR technology kept maturing, the Virtual Reconfigurable Circuit (VRC). In essence, a VRC in an FPGA is a virtual layer acting as an application specific reconfigurable circuit on top of an FPGA fabric that reduces the complexity of the reconfiguration process and increases its speed (compared to native reconfiguration). It is an array of computational nodes specified using standard HDL descriptions that define ad-hoc reconfigurable resources; routing multiplexers and a set of configurable processing elements, each one containing all the required functions, which are selectable through functionality multiplexers as in microprocessor ALUs. A large register acts as configuration memory, so VRC reconfiguration is very fast given it only involves writing this register, which drives the selection signals of the set of multiplexers. However, large overheads are introduced by this virtual layer; an area overhead due to the simultaneous implementation of every function in every node of the array plus the multiplexers, and a delay overhead due to the multiplexers, which also reduces maximum frequency of operation. The very nature of Evolvable Hardware, able to optimise its own computational behaviour, makes it a good candidate to advance research in self-adaptive systems. Combining a selfreconfigurable computing substrate able to be dynamically changed at run-time with an embedded algorithm that provides a direction for change, can help fulfilling requirements for autonomous lifetime adaptation of FPGA-based embedded systems. The main proposal of this thesis is hence directed to contribute to autonomous self-adaptation of the underlying computational hardware of FPGA-based embedded systems by means of Evolvable Hardware. This is tackled by considering that the computational behaviour of a system can be modified by changing any of its two constituent parts: an underlying hard structure and a set of soft parameters. Two main lines of work derive from this distinction. On one side, parametric self-adaptation and, on the other side, structural self-adaptation. The goal pursued in the case of parametric self-adaptation is the implementation of complex evolutionary optimisation techniques in resource constrained embedded systems for online parameter adaptation of signal processing circuits. The application selected as proof of concept is the optimisation of Discrete Wavelet Transforms (DWT) filters coefficients for very specific types of images, oriented to image compression. Hence, adaptive and improved compression efficiency, as compared to standard techniques, is the required goal of evolution. The main quest lies in reducing the supercomputing resources reported in previous works for the optimisation process in order to make it suitable for embedded systems. Regarding structural self-adaptation, the thesis goal is the implementation of self-adaptive circuits in FPGA-based evolvable systems through an efficient use of native reconfiguration capabilities. In this case, evolution of image processing tasks such as filtering of unknown and changing types of noise and edge detection are the selected proofs of concept. In general, evolving unknown image processing behaviours (within a certain complexity range) at design time is the required goal. In this case, the mission of the proposal is the incorporation of DPR in EHW to evolve a systolic array architecture adaptable through reconfiguration whose evolvability had not been previously checked. In order to achieve the two stated goals, this thesis originally proposes an evolvable platform that integrates an Adaptation Engine (AE), a Reconfiguration Engine (RE) and an adaptable Computing Engine (CE). In the case of parametric adaptation, the proposed platform is characterised by: ��� a CE featuring a DWT hardware processing core adaptable through reconfigurable registers that holds wavelet filters coefficients ��� an evolutionary algorithm as AE that searches for candidate wavelet filters through a parametric optimisation process specifically developed for systems featured by scarce computing resources ��� a new, simplified mutation operator for the selected EA, that together with a fast evaluation mechanism of candidate wavelet filters derived from existing literature, assures the feasibility of the evolutionary search involved in wavelets adaptation In the case of structural adaptation, the platform proposal takes the form of: ��� a CE based on a reconfigurable 2D systolic array template composed of reconfigurable processing nodes ��� an evolutionary algorithm as AE that searches for candidate configurations of the array using a set of computational functionalities for the nodes available in a run time accessible library ��� a hardware RE that exploits native DPR capabilities of FPGAs and makes an efficient use of the available reconfigurable resources of the device to change the behaviour of the CE at run time ��� a library of reconfigurable processing elements featured by position-independent partial bitstreams used as the set of available configurations for the processing nodes of the array Main contributions of this thesis can be summarised in the following list. ��� An FPGA-based evolvable platform for parametric and structural self-adaptation of embedded systems composed of a Computing Engine, an evolutionary Adaptation Engine and a Reconfiguration Engine. This platform is further developed and tailored for both parametric and structural self-adaptation. ��� Regarding parametric self-adaptation, main contributions are: ��� A CE adaptable through reconfigurable registers that enables parametric adaptation of the coefficients of an adaptive hardware implementation of a DWT core. ��� An AE based on an Evolutionary Algorithm specifically developed for numerical optimisation applied to wavelet filter coefficients in resource constrained embedded systems. ��� A run-time self-adaptive DWT IP core for embedded systems that allows for online optimisation of transform performance for image compression for specific deployment environments characterised by different types of input signals. ��� A software model and hardware implementation of a tool for the automatic, evolutionary construction of custom wavelet transforms. ��� Lastly, regarding structural self-adaptation, main contributions are: ��� A CE adaptable through native FPGA fabric reconfiguration featured by a two dimensional systolic array template of reconfigurable processing nodes. Different processing behaviours can be automatically mapped in the array by using a library of simple reconfigurable processing elements. ��� Definition of a library of such processing elements suited for autonomous runtime synthesis of different image processing tasks. ��� Efficient incorporation of DPR in EHW systems, overcoming main drawbacks from the previous approach of virtual reconfigurable circuits. Implementation details for both approaches are also originally compared in this work. ��� A fault tolerant, self-healing platform that enables online functional recovery in hazardous environments. The platform has been characterised from a fault tolerance perspective: fault models at FPGA CLB level and processing elements level are proposed, and using the RE, a systematic fault analysis for one fault in every processing element and for two accumulated faults is done. ��� A dynamic filtering quality platform that permits on-line adaptation to different types of noise and different computing behaviours considering the available computing resources. On one side, non-destructive filters are evolved, enabling scalable cascaded filtering schemes; and on the other, size-scalable filters are also evolved considering dynamically changing computational filtering requirements. This dissertation is organized in four parts and nine chapters. First part contains chapter 1, the introduction to and motivation of this PhD work. Following, the reference framework in which this dissertation is framed is analysed in the second part: chapter 2 features an introduction to the notions of self-adaptation and autonomic computing as a more general research field to the very specific one of this work; chapter 3 introduces evolutionary computation as the technique to drive adaptation; chapter 4 analyses platforms for reconfigurable computing as the technology to hold self-adaptive hardware; and finally chapter 5 defines, classifies and surveys the field of Evolvable Hardware. Third part of the work follows, which contains the proposal, development and results obtained: while chapter 6 contains an statement of the thesis goals and the description of the proposal as a whole, chapters 7 and 8 address parametric and structural self-adaptation, respectively. Finally, chapter 9 in part 4 concludes the work and describes future research paths.