Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform

One of the main concerns of evolvable and adaptive systems is the need of a training mechanism, which is normally done by using a training reference and a test input. The fitness function to be optimized during the evolution (training) phase is obtained by comparing the output of the candidate systems against the reference. The adaptivity that this type of systems may provide by re-evolving during operation is especially important for applications with runtime variable conditions. However, fully automated self-adaptivity poses additional problems. For instance, in some cases, it is not possible to have such reference, because the changes in the environment conditions are unknown, so it becomes difficult to autonomously identify which problem requires to be solved, and hence, what conditions should be representative for an adequate re-evolution. In this paper, a solution to solve this dependency is presented and analyzed. The system consists of an image filter application mapped on an evolvable hardware platform, able to evolve using two consecutive frames from a camera as both test and reference images. The system is entirely mapped in an FPGA, and native dynamic and partial reconfiguration is used for evolution. It is also shown that using such images, both of them being noisy, as input and reference images in the evolution phase of the system is equivalent or even better than evolving the filter with offline images. The combination of both techniques results in the completely autonomous, noise type/level agnostic filtering system without reference image requirement described along the paper.

A self-adaptive image processing application based on evolvable and scalable hardware

Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications.

A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

A scalable evolvable hardware processing array

Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits self-adaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case.

Combining Text and Graphics for Interactive Exploration of Behavior Datasets

Modern sensor technologies and simulators applied to large and complex dynamic systems (such as road traffic networks, sets of river channels, etc.) produce large amounts of behavior data that are difficult for users to interpret and analyze. Software tools that generate presentations combining text and graphics can help users understand this data. In this paper we describe the results of our research on automatic multimedia presentation generation (including text, graphics, maps, images, etc.) for interactive exploration of behavior datasets. We designed a novel user interface that combines automatically generated text and graphical resources. We describe the general knowledge-based design of our presentation generation tool. We also present applications that we developed to validate the method, and a comparison with related work.

Aprendizaje, simulación y desarrollo sobre las tecnologías de voz y datos

El objetivo del Proyecto Fin de Carrera (PFC) es el de conocer, simular y crear una red VoIP sobre una red de datos en un entorno docente, más concretamente, en la asignatura Redes y Servicios de telecomunicación en Grado en Ingeniería de Telecomunicaciones en la Universidad Politécnica de Madrid (UPM). Una vez se adquieran los conocimientos necesarios, se propondrán una serie de prácticas para que los alumnos se vayan familiarizando con el software y hardware utilizados, de manera que, se irá subiendo el grado de dificultad hasta que puedan realizar una auténtica red VoIP por sí mismos. A parte de la realización de las prácticas, los alumnos deberán pasar una prueba de los conocimientos adquiridos al final de cada práctica mediante preguntas tipo test. Los sistemas elegidos para la implantación de una red VoIP en los módulos de laboratorio son: 3CX System Phone y Asteisk-Trixbox. Los cuales, son capaces de trabajar mediante gestores gráficos para simplificar el nivel de dificultad de la configuración. 3CX es una PBX que trabaja sobre Windows y se basa exclusivamente en el protocolo SIP. Esto facilita el manejo para usuarios que solo han usado Windows sin quitar funcionalidades que tienen otras centralitas en otros sistemas operativos. La versión demo activa todas las opciones para poder familiarizarse con este sistema. Por otro lado, Asterisk trabaja en todas las plataformas, aunque se ha seleccionado trabajar sobre Linux. Esta selección se ha realizado porque el resto de plataformas limitan la configuración de la IP PBX, esta es de código abierto y permite realizar todo tipo de configuraciones. Además, es un software gratuito, esto es una ventaja a la hora de configurar novedades o resolver problemas, ya que hay muchos especialistas que dan soporte y ayudan de forma gratuita. La voz sobre Internet es habitualmente conocida como VoIP (Voice Over IP), debido a que IP (Internet Protocol) es el protocolo de red de Internet. Como tecnología, la VoIP no es solo un paso más en el crecimiento de las comunicaciones por voz, sino que supone integrar las comunicaciones de datos y las de voz en una misma red, y en concreto, en la red con mayor cobertura mundial: Internet. La mayor importancia y motivación de este Proyecto Fin de Carrera es que el alumno sea capaz de llegar a un entorno laboral y pueda tener unos conocimientos capaces de afrontar esta tecnología que esta tan a la orden del día. La importancia que estas redes tienen y tendrán en un futuro muy próximo en el mundo de la informática y las comunicaciones. Cabe decir, que se observa que estas disciplinas tecnológicas evolucionan a pasos agigantados y se requieren conocimientos más sólidos. ABSTRACT. The objective of my final project during my studies in university was, to simulate and create a VoIP network over a data network in a teaching environment, more specifically on the subject of telecommunications networks and services in Telecommunication Engineering Degree in Polytechnic University of Madrid (UPM). Once acquiring the necessary knowledge a number of practices were proposed to the students to become familiar with the software and hardware used, so that it would rise to the level of difficulty that they could make a real VoIP network for themselves. Parts of the experimental practices were that students must pass a test of knowledge acquired at the end of each practice by choice questions. The systems chosen for the implementation of a VoIP network in the laboratory modules are: 3CX Phone System and Asteisk - Trixbox. Which were able to work with graphics operators to simplify the difficulty level of the configuration. 3CX is a PBX that works on Windows and is based solely on the SIP protocol. This facilitates handling for users who have only used Windows without removing functionality with other exchanges in other operating systems. Active demo version all options to get to grips with this system. Moreover, Asterisk works on all platforms, but has been selected to work on Linux. This selection was made because other platforms limit the IP PBX configuration, as this is open source and allows all kinds of configurations. Also, Linux is a free software and an advantage when configuring new or solve problems, as there are many specialists that support and help for free. Voice over Internet is commonly known as VoIP (Voice Over IP), because IP (Internet Protocol) is the Internet protocol network. As technology, VoIP is not just another step in the growth of voice communications, but communications of integrating data and voice on a single network, and in particular, in the network with the largest global coverage: Internet. The increased importance and motivation of this Thesis is that the student is able to reach a working environment and may have some knowledge to deal with these technologies that is so much the order of the day. The importances of these networks have and will be of essences in the very near future in the world of computing and communications. It must be said it is observed that these technological disciplines evolve by leaps and bounds stronger knowledge required.

Desarrollo de un sistema hardware modular que implemente los instrumentos de un laboratorio de electrónica

El poder disponer de la instrumentación y los equipos electrónicos resulta vital en el diseño de circuitos analógicos. Permiten realizar las pruebas necesarias y el estudio para el buen funcionamiento de estos circuitos. Los equipos se pueden diferenciar en instrumentos de excitación, los que proporcionan las señales al circuito, y en instrumentos de medida, los que miden las señales generadas por el circuito. Estos equipos sirven de gran ayuda pero a su vez tienen un precio elevado lo que impide en muchos casos disponer de ellos. Por esta principal desventaja, se hace necesario conseguir un dispositivo de bajo coste que sustituya de alguna manera a los equipos reales. Si el instrumento es de medida, este sistema de bajo coste puede ser implementado mediante un equipo hardware encargado de adquirir los datos y una aplicación ejecutándose en un ordenador donde analizarlos y presentarlos en la pantalla. En el caso de que el instrumento sea de excitación, el único cometido del sistema hardware es el de proporcionar las señales cuya configuración ha enviado el ordenador. En un equipo real, es el propio equipo el que debe realizar todas esas acciones: adquisición, procesamiento y presentación de los datos. Además, la dificultad de realizar modificaciones o ampliaciones de las funcionalidades en un instrumento tradicional con respecto a una aplicación de queda patente. Debido a que un instrumento tradicional es un sistema cerrado y uno cuya configuración o procesamiento de datos es hecho por una aplicación, algunas de las modificaciones serían realizables modificando simplemente el software del programa de control, por lo que el coste de las modificaciones sería menor. En este proyecto se pretende implementar un sistema hardware que tenga las características y realice las funciones del equipamiento real que se pueda encontrar en un laboratorio de electrónica. También el desarrollo de una aplicación encargada del control y el análisis de las señales adquiridas, cuya interfaz gráfica se asemeje a la de los equipos reales para facilitar su uso. ABSTRACT. The instrumentation and electronic equipment are vital for the design of analogue circuits. They enable to perform the necessary testing and study for the proper functioning of these circuits. The devices can be classified into the following categories: excitation instruments, which transmit the signals to the circuit, and measuring instruments, those in charge of measuring the signals produced by the circuit. This equipment is considerably helpful, however, its high price often makes it hardly accessible. For this reason, low price equipment is needed in order to replace real devices. If the instrument is measuring, this low cost system can be implemented by hardware equipment to acquire the data and running on a computer where analyzing and present on the screen application. In case of an excitation the instrument, the only task of the hardware system is to provide signals which sent the computer configuration. In a real instrument, is the instrument itself that must perform all these actions: acquisition, processing and presentation of data. Moreover, the difficulty of making changes or additions to the features in traditional devices with respect to an application running on a computer is evident. This is due to the fact that a traditional instrument is a closed system and its configuration or data processing is made by an application. Therefore, certain changes can be made just by modifying the control program software. Consequently, the cost of these modifications is lower. This project aims to implement a hardware system with the same features and functions of any real device, available in an electronics laboratory. Besides, it aims to develop an application for the monitoring and analysis of acquired signals. This application is provided with a graphic interface resembling those of real devices in order to facilitate its use.

Novel educational assessment for building structures: Automatic evaluation of on-line graphics

This article presents a new automatic evaluation for on-line graphics, its application and the numerous advantages achieved applying this developed correcting method. The software application developed by the Innovation in Education Group “E4”, from the Technical University of Madrid, is oriented for the online self-assessment of the graphic drawings that students carry out as continuous training. The adaptation to the European Higher Educational Area is an important opportunity to research about the possibilities of on-line education assessment. In this way, a new software tool has been developed for continuous self-testing by undergraduates. Using this software it is possible to evaluate the graphical answer of the students. Thus, the drawings made on-line by students are automatically corrected according to the geometry (straight lines, sloping lines or second order curves) and by sizes (depending on the specific values which define the graphics).

Towards a unified sentiment lexicon based on graphics processing units

This paper presents an approach to create what we have called a Unified Sentiment Lexicon (USL). This approach aims at aligning, unifying, and expanding the set of sentiment lexicons which are available on the web in order to increase their robustness of coverage. One problem related to the task of the automatic unification of different scores of sentiment lexicons is that there are multiple lexical entries for which the classification of positive, negative, or neutral {P, Z, N} depends on the unit of measurement used in the annotation methodology of the source sentiment lexicon. Our USL approach computes the unified strength of polarity of each lexical entry based on the Pearson correlation coefficient which measures how correlated lexical entries are with a value between 1 and -1, where 1 indicates that the lexical entries are perfectly correlated, 0 indicates no correlation, and -1 means they are perfectly inversely correlated and so is the UnifiedMetrics procedure for CPU and GPU, respectively. Another problem is the high processing time required for computing all the lexical entries in the unification task. Thus, the USL approach computes a subset of lexical entries in each of the 1344 GPU cores and uses parallel processing in order to unify 155802 lexical entries. The results of the analysis conducted using the USL approach show that the USL has 95.430 lexical entries, out of which there are 35.201 considered to be positive, 22.029 negative, and 38.200 neutral. Finally, the runtime was 10 minutes for 95.430 lexical entries; this allows a reduction of the time computing for the UnifiedMetrics by 3 times.

Hardware timestamping for image acquisition system based on FlexRIO and IEEE 1588 v2 Standard

Current fusion devices consist of multiple diagnostics and hundreds or even thousands of signals. This situation forces on multiple occasions to use distributed data acquisition systems as the best approach. In this type of distributed systems, one of the most important issues is the synchronization between signals, so that it is possible to have a temporal correlation as accurate as possible between the acquired samples of all channels. In last decades, many fusion devices use different types of video cameras to provide inside views of the vessel during operations and to monitor plasma behavior. The synchronization between each video frame and the rest of the different signals acquired from any other diagnostics is essential in order to know correctly the plasma evolution, since it is possible to analyze jointly all the information having accurate knowledge of their temporal correlation. The developed system described in this paper allows timestamping image frames in a real-time acquisition and processing system using 1588 clock distribution. The system has been implemented using FPGA based devices together with a 1588 synchronized timing card (see Fig.1). The solution is based on a previous system [1] that allows image acquisition and real-time image processing based on PXIe technology. This architecture is fully compatible with the ITER Fast Controllers [2] and offers integration with EPICS to control and monitor the entire system. However, this set-up is not able to timestamp the frames acquired since the frame grabber module does not present any type of timing input (IRIG-B, GPS, PTP). To solve this lack, an IEEE1588 PXI timing device its used to provide an accurate way to synchronize distributed data acquisition systems using the Precision Time Protocol (PTP) IEEE 1588 2008 standard. This local timing device can be connected to a master clock device for global synchronization. The timing device has a buffer timestamp for each PXI trigger line and requires tha- a software application assigns each frame the corresponding timestamp. The previous action is critical and cannot be achieved if the frame rate is high. To solve this problem, it has been designed a solution that distributes the clock from the IEEE 1588 timing card to all FlexRIO devices [3]. This solution uses two PXI trigger lines that provide the capacity to assign timestamps to every frame acquired and register events by hardware in a deterministic way. The system provides a solution for timestamping frames to synchronize them with the rest of the different signals.

Elementos de sistemas operativos, de representación de la información y de procesadores hardware y software

Conceptos de representación binaria y de arquitecturas hardware y software con prácticas de laboratorio sobre Linux y ejercicios resueltos.

3D simulation of complex shading affecting PV systems taking benefit from the power of graphics cards developed for the video game industry

Shading reduces the power output of a photovoltaic (PV) system. The design engineering of PV systems requires modeling and evaluating shading losses. Some PV systems are affected by complex shading scenes whose resulting PV energy losses are very difficult to evaluate with current modeling tools. Several specialized PV design and simulation software include the possibility to evaluate shading losses. They generally possess a Graphical User Interface (GUI) through which the user can draw a 3D shading scene, and then evaluate its corresponding PV energy losses. The complexity of the objects that these tools can handle is relatively limited. We have created a software solution, 3DPV, which allows evaluating the energy losses induced by complex 3D scenes on PV generators. The 3D objects can be imported from specialized 3D modeling software or from a 3D object library. The shadows cast by this 3D scene on the PV generator are then directly evaluated from the Graphics Processing Unit (GPU). Thanks to the recent development of GPUs for the video game industry, the shadows can be evaluated with a very high spatial resolution that reaches well beyond the PV cell level, in very short calculation times. A PV simulation model then translates the geometrical shading into PV energy output losses. 3DPV has been implemented using WebGL, which allows it to run directly from a Web browser, without requiring any local installation from the user. This also allows taken full benefits from the information already available from Internet, such as the 3D object libraries. This contribution describes, step by step, the method that allows 3DPV to evaluate the PV energy losses caused by complex shading. We then illustrate the results of this methodology to several application cases that are encountered in the world of PV systems design. Keywords: 3D, modeling, simulation, GPU, shading, losses, shadow mapping, solar, photovoltaic, PV, WebGL

A proposal for an Internet of Things-based monitoring system composed by low capability, open source and open hardware devices

The Internet of Things makes use of a huge disparity of technologies at very different levels that help one to the other to accomplish goals that were previously regarded as unthinkable in terms of ubiquity or scalability. If the Internet of Things is expected to interconnect every day devices or appliances and enable communications between them, a broad range of new services, applications and products can be foreseen. For example, monitoring is a process where sensors have widespread use for measuring environmental parameters (temperature, light, chemical agents, etc.) but obtaining readings at the exact physical point they want to be obtained from, or about the exact wanted parameter can be a clumsy, time-consuming task that is not easily adaptable to new requirements. In order to tackle this challenge, a proposal on a system used to monitor any conceivable environment, which additionally is able to monitor the status of its own components and heal some of the most usual issues of a Wireless Sensor Network, is presented here in detail, covering all the layers that give it shape in terms of devices, communications or services.

Collaborative Evolution Strategies on Evolvable Hardware Networked Elements

Dynamic and Partial Reconfiguration allows systems to change some parts of their hardware at run time. This feature favours the inclusion of evolutionary strategies to provide optimised solutions to the same problem so that they can be mixed and compared in a way that only the best ones prevail. At the same time, distributed intelligence permits systems to work in a collaborative way to jointly improve their global capabilities. This work presents a combination of both approaches where hardware evolution is performed both at local and network level in order to improve an image filter application in terms of performance, robustness and providing the capacity of avoiding local minimums, which is the main drawback of some evolutionary approaches.

Development of Brain-Computer Interfaces using Evolvable Hardware

Brain-Computer Interfaces are usually tackled from a medical point of view, correlating observed phenomena to physical facts known about the brain. Existing methods of classification lie in the application of deterministic algorithms and depend on certain degree of knowledge about the underlying phenomena so as to process data. In this demo, different architectures for an evolvable hardware classifier implemented on an FPGA are proposed, in line with the objective of generalizing evolutionary algorithms regardless of the application.