Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

Over Expression of the CMP-sialic Acid Transporter in Chinese Hamster Ovary Cells Leads to Increased Sialylation

Most glyco-engineering approaches used to improve quality of recombinant glycoproteins involve the manipulation of glycosyltransferase and/or glycosidase expression. We investigated whether the over expression of nucleotide sugar transporters, particularly the CMP-sialic acid transporter (CMP-SAT), would be a means to improve the sialylation process in CHO cells. We hypothesized that increasing the expression of the CMP-SAT in the cells would increase the transport of the CMP-sialic acid in the Golgi lumen, hence increasing the intra-lumenal CMP-sialic acid pool, and resulting in a possible increase in sialylation extent of proteins being produced. We report the construction of a CMP-SAT expression vector which was used for transfection into CHO-IFNγ, a CHO cell line producing human IFNγ. This resulted in approximately 2 to 5 times increase in total CMP-SAT expression in some of the positive clones as compared to untransfected CHO-IFNγ, as determined using real-time PCR analysis. This in turn concurred with a 9.6% to 16.3% percent increase in site sialylation. This engineering approach has thus been identified as a novel means of improving sialylation in recombinant glycoprotein therapeutics. This strategy can be utilized feasibly on its own, or in combination with existing sialylation improvement strategies. It is believed that such multi-prong approaches are required to effectively manipulate the complex sialylation process, so as to bring us closer to the goal of producing recombinant glycoproteins of high and consistent sialylation from mammalian cells.