2 resultados para Metal stamping tools

em Massachusetts Institute of Technology


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In early stages of architectural design, as in other design domains, the language used is often very abstract. In architectural design, for example, architects and their clients use experiential terms such as "private" or "open" to describe spaces. If we are to build programs that can help designers during this early-stage design, we must give those programs the capability to deal with concepts on the level of such abstractions. The work reported in this thesis sought to do that, focusing on two key questions: How are abstract terms such as "private" and "open" translated into physical form? How might one build a tool to assist designers with this process? The Architect's Collaborator (TAC) was built to explore these issues. It is a design assistant that supports iterative design refinement, and that represents and reasons about how experiential qualities are manifested in physical form. Given a starting design and a set of design goals, TAC explores the space of possible designs in search of solutions that satisfy the goals. It employs a strategy we've called dependency-directed redesign: it evaluates a design with respect to a set of goals, then uses an explanation of the evaluation to guide proposal and refinement of repair suggestions; it then carries out the repair suggestions to create new designs. A series of experiments was run to study TAC's behavior. Issues of control structure, goal set size, goal order, and modification operator capabilities were explored. In addition, TAC's use as a design assistant was studied in an experiment using a house in the process of being redesigned. TAC's use as an analysis tool was studied in an experiment using Frank Lloyd Wright's Prairie houses.

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Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁₋xGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented.