The Inertio-Elastic Planar Entry Flow of Low-Viscosity Elastic Fluids in Micro-fabricated Geometries

The non-Newtonian flow of dilute aqueous polyethylene oxide (PEO) solutions through microfabricated planar abrupt contraction-expansions is investigated. The contraction geometries are fabricated from a high-resolution chrome mask and cross-linked PDMS gels using the tools of soft-lithography. The small length scales and high deformation rates in the contraction throat lead to significant extensional flow effects even with dilute polymer solutions having time constants on the order of milliseconds. The dimensionless extra pressure drop across the contraction increases by more than 200% and is accompanied by significant upstream vortex growth. Streak photography and videomicroscopy using epifluorescent particles shows that the flow ultimately becomes unstable and three-dimensional. The moderate Reynolds numbers (0.03 ≤ Re ≤ 44) associated with these high Deborah number (0 ≤ De ≤ 600) microfluidic flows results in the exploration of new regions of the Re-De parameter space in which the effects of both elasticity and inertia can be observed. Understanding such interactions will be increasingly important in microfluidic applications involving complex fluids and can best be interpreted in terms of the elasticity number, El = De/Re, which is independent of the flow kinematics and depends only on the fluid rheology and the characteristic size of the device.

Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques.