Implementation Workshop: High Performance Work Organizations

Since the rise of the industrial revolution, there are few challenges that compare in scale and scope with the challenge of implementing lean principles in order to achieve high performance work systems. This report summarize key insights and learning by representatives from a cross section of organizations who are on this journey. Specifically, we report on findings from the first Lean Aircraft Initiative (LAI) Implementation Workshop, which was held on February 5-6, 1997.

Implementation Workshop: High Performance Work Organizations

Since the rise of the industrial revolution, there are few challenges that compare in scale and scope with the challenge of implementing lean principles in order to achieve high performance work systems. This report summarize key insights and learning by representatives from a cross section of organizations who are on this journey. Specifically, we report on findings from the first Lean Aircraft Initiative (LAI) Implementation Workshop, which was held on February 5-6, 1997. The report is not a “cookbook” or a “how to” manual. Rather, it is a summary of the first phase in a learning process. It is designed to codify lessons learning, facilitate diffusion among people not at the session, and set the stage for further learning about implementation.

Fast Sorting on a Distributed-Memory Architecture

We consider the often-studied problem of sorting, for a parallel computer. Given an input array distributed evenly over p processors, the task is to compute the sorted output array, also distributed over the p processors. Many existing algorithms take the approach of approximately load-balancing the output, leaving each processor with Θ(n/p) elements. However, in many cases, approximate load-balancing leads to inefficiencies in both the sorting itself and in further uses of the data after sorting. We provide a deterministic parallel sorting algorithm that uses parallel selection to produce any output distribution exactly, particularly one that is perfectly load-balanced. Furthermore, when using a comparison sort, this algorithm is 1-optimal in both computation and communication. We provide an empirical study that illustrates the efficiency of exact data splitting, and shows an improvement over two sample sort algorithms.

Performance Evaluation of the Scheme 86 and HP Precision Architecture

The Scheme86 and the HP Precision Architectures represent different trends in computer processor design. The former uses wide micro-instructions, parallel hardware, and a low latency memory interface. The latter encourages pipelined implementation and visible interlocks. To compare the merits of these approaches, algorithms frequently encountered in numerical and symbolic computation were hand-coded for each architecture. Timings were done in simulators and the results were evaluated to determine the speed of each design. Based on these measurements, conclusions were drawn as to which aspects of each architecture are suitable for a high- performance computer.