Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.

Investigation of aspect ratio of hole drilling from micro to nanoscale via focused ion beam fine milling

Holes with different sizes from microscale to nanoscale were directly fabricated by focused ion beam (FIB) milling in this paper. Maximum aspect ratio of the fabricated holes can be 5:1 for the hole with large size with pure FIB milling, 10:1 for gas assistant etching, and 1:1 for the hole with size below 100 nm. A phenomenon of volume swell at the boundary of the hole was observed. The reason maybe due to the dose dependence of the effective sputter yield in low intensity Gaussian beam tail regions and redeposition. Different materials were used to investigate variation of the aspect ratio. The results show that for some special material, such as Ni-Be, the corresponding aspect ratio can reach 13.8:1 with Cl₂ assistant etching, but only 0.09:1 for Si(100) with single scan of the FIB.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

A Two-level Prediction Model for Deep Reactive Ion Etch (DRIE)

We contribute a quantitative and systematic model to capture etch non-uniformity in deep reactive ion etch of microelectromechanical systems (MEMS) devices. Deep reactive ion etch is commonly used in MEMS fabrication where high-aspect ratio features are to be produced in silicon. It is typical for many supposedly identical devices, perhaps of diameter 10 mm, to be etched simultaneously into one silicon wafer of diameter 150 mm. Etch non-uniformity depends on uneven distributions of ion and neutral species at the wafer level, and on local consumption of those species at the device, or die, level. An ion–neutral synergism model is constructed from data obtained from etching several layouts of differing pattern opening densities. Such a model is used to predict wafer-level variation with an r.m.s. error below 3%. This model is combined with a die-level model, which we have reported previously, on a MEMS layout. The two-level model is shown to enable prediction of both within-die and wafer-scale etch rate variation for arbitrary wafer loadings.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

Tubular Organization of SnO₂ Nanocrystallites for Improved Lithium Ion Battery Anode Performance

Porous tin oxide nanotubes were obtained by vacuum infiltration of tin oxide nanoparticles into porous aluminum oxide membranes, followed by calcination. The porous tin oxide nanotube arrays so prepared were characterized by FE-SEM, TEM, HRTEM, and XRD. The nanotubes are open-ended, highly ordered with uniform cross-sections, diameters and wall thickness. The tin oxide nanotubes were evaluated as a substitute anode material for the lithium ion batteries. The tin oxide nanotube anode could be charged and discharged repeatedly, retaining a specific capacity of 525 mAh/g after 80 cycles. This capacity is significantly higher than the theoretical capacity of commercial graphite anode (372 mAh/g) and the cyclability is outstanding for a tin based electrode. The cyclability and capacities of the tin oxide nanotubes were also higher than their building blocks of solid tin oxide nanoparticles. A few factors accounting for the good cycling performance and high capacity of tin oxide nanotubes are suggested.