Over Expression of the CMP-sialic Acid Transporter in Chinese Hamster Ovary Cells Leads to Increased Sialylation

Most glyco-engineering approaches used to improve quality of recombinant glycoproteins involve the manipulation of glycosyltransferase and/or glycosidase expression. We investigated whether the over expression of nucleotide sugar transporters, particularly the CMP-sialic acid transporter (CMP-SAT), would be a means to improve the sialylation process in CHO cells. We hypothesized that increasing the expression of the CMP-SAT in the cells would increase the transport of the CMP-sialic acid in the Golgi lumen, hence increasing the intra-lumenal CMP-sialic acid pool, and resulting in a possible increase in sialylation extent of proteins being produced. We report the construction of a CMP-SAT expression vector which was used for transfection into CHO-IFNγ, a CHO cell line producing human IFNγ. This resulted in approximately 2 to 5 times increase in total CMP-SAT expression in some of the positive clones as compared to untransfected CHO-IFNγ, as determined using real-time PCR analysis. This in turn concurred with a 9.6% to 16.3% percent increase in site sialylation. This engineering approach has thus been identified as a novel means of improving sialylation in recombinant glycoprotein therapeutics. This strategy can be utilized feasibly on its own, or in combination with existing sialylation improvement strategies. It is believed that such multi-prong approaches are required to effectively manipulate the complex sialylation process, so as to bring us closer to the goal of producing recombinant glycoproteins of high and consistent sialylation from mammalian cells.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.