Time-Precision Flexible Adder
| Contribuinte(s) |
Universidad de Alicante. Departamento de Tecnología Informática y Computación Informática Industrial y Redes de Computadores |
|---|---|
| Data(s) |
03/03/2015
03/03/2015
2003
|
| Resumo |
Paper submitted to 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sharjah, Emiratos Árabes, 2003. A new conception of flexible calculation that allows us to adjust a sum depending on the available time computation is presented. More specifically, the objective is to obtain a calculation model that makes the processing time/precision more flexible. The addition method is based on carry-select scheme adder and the proposed design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design. This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government. |
| Identificador |
Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003. Vol. 3. IEEE, 2003. ISBN 0-7803-8163-7, pp. 994-997 0-7803-8163-7 http://hdl.handle.net/10045/45454 10.1109/ICECS.2003.1301676 |
| Idioma(s) |
eng |
| Publicador |
IEEE |
| Relação |
http://dx.doi.org/10.1109/ICECS.2003.1301676 |
| Direitos |
© 2003 IEEE info:eu-repo/semantics/openAccess |
| Palavras-Chave | #Application specific architectures #Look-up tables #Specialized architecture #Adder #Arquitectura y Tecnología de Computadores |
| Tipo |
info:eu-repo/semantics/conferenceObject |
