A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs
Data(s) |
01/09/2011
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Resumo |
A highly parallel and scalable Deblocking Filter (DF) hardware architecture for H.264/AVC and SVC video codecs is presented in this paper. The proposed architecture mainly consists on a coarse grain systolic array obtained by replicating a unique and homogeneous Functional Unit (FU), in which a whole Deblocking-Filter unit is implemented. The proposal is also based on a novel macroblock-level parallelization strategy of the filtering algorithm which improves the final performance by exploiting specific data dependences. This way communication overhead is reduced and a more intensive parallelism in comparison with the existing state-of-the-art solutions is obtained. Furthermore, the architecture is completely flexible, since the level of parallelism can be changed, according to the application requirements. The design has been implemented in a Virtex-5 FPGA, and it allows filtering 4CIF (704 × 576 pixels @30 fps) video sequences in real-time at frequencies lower than 10.16 Mhz. |
Formato |
application/pdf |
Identificador | |
Idioma(s) |
eng |
Relação |
http://oa.upm.es/12900/1/INVE_MEM_2011_108099.pdf http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6012075 info:eu-repo/semantics/altIdentifier/doi/null |
Direitos |
http://creativecommons.org/licenses/by-nc-nd/3.0/es/ info:eu-repo/semantics/openAccess |
Fonte |
Proceedings of 2011 IEEE International Conference on Multimedia and Expo (ICME) | 2011 IEEE International Conference on Multimedia and Expo (ICME) | 11/07/2011 - 15/07/2011 | Barcelona, España |
Palavras-Chave | #Informática #Física |
Tipo |
info:eu-repo/semantics/conferenceObject Ponencia en Congreso o Jornada PeerReviewed |