Checking Completeness of Tests for Finite State Machines
| Contribuinte(s) |
UNIVERSIDADE DE SÃO PAULO |
|---|---|
| Data(s) |
20/10/2012
20/10/2012
2010
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| Resumo |
In testing from a Finite State Machine (FSM), the generation of test suites which guarantee full fault detection, known as complete test suites, has been a long-standing research topic. In this paper, we present conditions that are sufficient for a test suite to be complete. We demonstrate that the existing conditions are special cases of the proposed ones. An algorithm that checks whether a given test suite is complete is given. The experimental results show that the algorithm can be used for relatively large FSMs and test suites. Natural Sciences and Engineering Research Council of Canada Natural Sciences and Engineering Research Council of Canada[OGP0194381] Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) CNPq[200032/2008-9] |
| Identificador |
IEEE TRANSACTIONS ON COMPUTERS, v.59, n.8, p.1023-1032, 2010 0018-9340 http://producao.usp.br/handle/BDPI/28989 10.1109/TC.2010.17 |
| Idioma(s) |
eng |
| Publicador |
IEEE COMPUTER SOC |
| Relação |
Ieee Transactions on Computers |
| Direitos |
restrictedAccess Copyright IEEE COMPUTER SOC |
| Palavras-Chave | #Finite State Machine #test analysis #fault coverage #test completeness conditions #test generation #SEQUENCES #SPECIFICATIONS #REDUCTION #LENGTH #DESIGN #Computer Science, Hardware & Architecture #Engineering, Electrical & Electronic |
| Tipo |
article original article publishedVersion |
