Median architecture by accumulative parallel counters


Autoria(s): Cadenas Medina, Jose; Megson, G. M.; Sherratt, Simon
Data(s)

01/07/2015

Resumo

The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

Formato

text

Identificador

http://centaur.reading.ac.uk/36577/1/APCMedian-TCAS-Centaur.pdf

Cadenas Medina, J. <http://centaur.reading.ac.uk/view/creators/90000433.html>, Megson, G. M. and Sherratt, S. <http://centaur.reading.ac.uk/view/creators/90000807.html> (2015) Median architecture by accumulative parallel counters. IEEE Transactions on Circuits and Systems II, Express Briefs, 62 (7). pp. 661-665. ISSN 1549-7747 doi: 10.1109/TCSII.2015.2415655 <http://dx.doi.org/10.1109/TCSII.2015.2415655>

Idioma(s)

en

Publicador

IEEE

Relação

http://centaur.reading.ac.uk/36577/

creatorInternal Cadenas Medina, Jose

creatorInternal Sherratt, Simon

10.1109/TCSII.2015.2415655

Tipo

Article

PeerReviewed