Rapid design of DSP ASIC cores using hierarchical VHDL libraries
| Data(s) |
01/01/1997
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| Resumo |
Methods are presented for the rapid design of DSP ASICs based on the use of a series of hierarchical VHDL libraries which are portable across many silicon foundries. These allows complex DSP silicon systems to be developed in a small fraction of the time normally required. Resulting designs are highly competitive with those developed using more conventional methods. The approach is illustrated using several examples. These include ADPCM codecs, as well as DCT and FFT cores. |
| Identificador | |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
McCanny , J V , Hu , Y , Ding , T J , Trainor , D & Ridge , D 1997 , Rapid design of DSP ASIC cores using hierarchical VHDL libraries . in Conference record of the 30th Asilomar Conference of Signals, Systems and Computers . vol. 2 , Institute of Electrical and Electronics Engineers (IEEE) , pp. 1344-1348 . DOI: 10.1109/ACSSC.1996.599167 |
| Tipo |
contributionToPeriodical |
| Publicador |
Institute of Electrical and Electronics Engineers (IEEE) |
