From bit level systolic arrays to HDTV processor chips
| Data(s) |
01/01/2006
|
|---|---|
| Identificador | |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
McCanny , J V , Woods , R F & McWhirter , J G 2006 , From bit level systolic arrays to HDTV processor chips . in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors . pp. 159-162 , 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors , Steamboat Springs, Co , United States , 1-1 September . DOI: 10.1109/ASAP.2006.35 |
| Tipo |
contributionToPeriodical |
| Resumo |
The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. © 2006 IEEE. |
| Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700 #Computer Science(all) |
