Hierarchical DSP architectural synthesis and scheduling solution for “IRIS”

Autoria(s): Yi, Y.; Woods, Roger; Turner, Richard
Data(s)

01/08/2003
Identificador

http://pure.qub.ac.uk/portal/en/publications/hierarchical-dsp-architectural-synthesis-and-scheduling-solution-for-iris(0786a03e-8bc7-40f5-93bf-83d6eabe4bc7).html
Idioma(s)

eng
Direitos

info:eu-repo/semantics/restrictedAccess
Fonte

Yi , Y , Woods , R & Turner , R 2003 , ' Hierarchical DSP architectural synthesis and scheduling solution for “IRIS” ' Paper presented at IEEE Workshop on Signal Processing Systems , Seoul , Korea, Republic of , 01/08/2003 - 01/08/2003 , pp. 375-380 .
Tipo

conferenceObject
Acesso ao item digital