Exploring Technology Related Design-Space Limitations of High Performance Network Processing
| Data(s) |
01/09/2007
|
|---|---|
| Identificador |
http://www.scopus.com/inward/record.url?scp=44849122279&partnerID=8YFLogxK |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
McCanny , J , Sezer , S & O'Neill , M 2007 , Exploring Technology Related Design-Space Limitations of High Performance Network Processing . in D SchmittLandsiedel & T Noll (eds) , ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE . Proceedings of the European Solid-State Circuits Conference , Institute of Electrical and Electronics Engineers (IEEE) , NEW YORK , pp. 222-231 , IEEE European Solid State Circuits Conference (ESSCIRC) , Munich , Germany , 1-1 September . |
| Tipo |
contributionToPeriodical |
| Contribuinte(s) |
SchmittLandsiedel, D Noll, T |
| Resumo |
<p>This paper summarizes numerous research activities in high-performance networks and network security processing, and explores technology related performance constraints such as critical performance limitations of circuit architectures, which are set by the semiconductor technologies.</p> |
| Publicador |
Institute of Electrical and Electronics Engineers (IEEE) |
