Architectural implications of nanoscale-integrated sensing and computing
Data(s) |
01/01/2010
|
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Formato |
110 - 120 |
Identificador |
IEEE Micro, 2010, 30 (1), pp. 110 - 120 0272-1732 |
Idioma(s) |
en_US |
Relação |
IEEE Micro 10.1109/MM.2010.9 |
Tipo |
Journal Article |
Resumo |
The authors explore nanoscale sensor processor (nSP) architectures. Their design includes a simple accumulator-based instruction-set architecture, sensors, limited memory, and instruction-fused sensing. Using nSP technology based on optical resonance energy transfer logic helps them decrease the design's size; their smallest design is about the size of the largest-known virus. © 2006 IEEE. |