Synchronous circuit verification by symbolic simulation: an illustration

Autoria(s): Derek L. Beatty; Randal E. Bryant; Carl-Johan H. Seger
Data(s)

1990
Identificador

http://ir.iscas.ac.cn/handle/311060/1355

http://www.irgrid.ac.cn/handle/1471x/66873
Idioma(s)

中文
Fonte

Derek L. Beatty , Randal E. Bryant , Carl-Johan H. Seger.Synchronous circuit verification by symbolic simulation: an illustration.见:Proceedings of the sixth MIT conference on Advanced research in VLSI .Boston, Massachusetts, United States .1990.
Tipo

会议论文
Acesso ao item digital