A communication model and partitioning algorithm for streaming applications for an embedded MPSoC


Autoria(s): Kelly, Wayne A.; Flasskamp, Martin; Sievers, Gregor; Ax, Johannes; Chen, Jianing; Klarhorst, Christian; Ragg, Christoph; Jungeblut, Thorsten; Sorensen, Andrew C.
Contribuinte(s)

Nurmi, Jari

Ellervee, Peeter

Milojevic, Dragomir

Daniel, Ondrej

Paakki, Tommi

Data(s)

2014

Resumo

Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulated-annealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%.

Identificador

http://eprints.qut.edu.au/80092/

Publicador

IEEE

Relação

DOI:10.1109/ISSOC.2014.6972436

Kelly, Wayne A., Flasskamp, Martin, Sievers, Gregor, Ax, Johannes, Chen, Jianing, Klarhorst, Christian, Ragg, Christoph, Jungeblut, Thorsten, & Sorensen, Andrew C. (2014) A communication model and partitioning algorithm for streaming applications for an embedded MPSoC. In Nurmi, Jari, Ellervee, Peeter, Milojevic, Dragomir, Daniel, Ondrej, & Paakki, Tommi (Eds.) Proceedings of the 2014 International Symposium on System-on-Chip (SoC), IEEE, Tampere, Finland, pp. 1-6.

Direitos

Copyright 2014 by IEEE

Fonte

School of Electrical Engineering & Computer Science; Science & Engineering Faculty

Palavras-Chave #Computer architecture #Parallel processing #Partitioning algorithms #Pipelines #Program processors #Signal processing algorithms #Simulated annealing
Tipo

Conference Paper