An FPGA-based approach to multi-objective evolutionary algorithm for multi-disciplinary design optimisation


Autoria(s): Kok, Jonathan; Gonzalez, Luis F.; Kelson, Neil A.; Periaux, Jacques
Contribuinte(s)

Poloni, C.

Quagliarella, D.

Periaux, J.

Gauger, N.

Giannakoglou, K.

Data(s)

03/10/2011

Resumo

This paper investigates the field programmable gate array (FPGA) approach for multi-objective and multi-disciplinary design optimisation (MDO) problems. One class of optimisation method that has been well-studied and established for large and complex problems, such as those inherited in MDO, is multi-objective evolutionary algorithms (MOEAs). The MOEA, nondominated sorting genetic algorithm II (NSGA-II), is hardware implemented on an FPGA chip. The NSGA-II on FPGA application to multi-objective test problem suites has verified the designed implementation effectiveness. Results show that NSGA-II on FPGA is three orders of magnitude better than the PC based counterpart.

Formato

application/pdf

Identificador

http://eprints.qut.edu.au/46292/

Publicador

CIMNE

Relação

http://eprints.qut.edu.au/46292/1/Eurogen2011.pdf

http://www.eurogen2011.cira.it/index.php?option=com_content&view=article&id=12&Itemid=1

Kok, Jonathan, Gonzalez, Luis F., Kelson, Neil A., & Periaux, Jacques (2011) An FPGA-based approach to multi-objective evolutionary algorithm for multi-disciplinary design optimisation. In Poloni, C., Quagliarella, D., Periaux, J., Gauger, N., & Giannakoglou, K. (Eds.) Evolutionary and Deterministic Methods for Design, Optimization and Control (Eurogen 2011), 14-16 September 2011, Italian Aerospace Research Center, Capua.

Direitos

Copyright 2011 [please consult the author]

Fonte

Australian Research Centre for Aerospace Automation; Division of Technology, Information and Learning Support; Faculty of Built Environment and Engineering; High Performance Computing and Research Support; School of Engineering Systems

Palavras-Chave #090100 AEROSPACE ENGINEERING #multi-objective optimisation #multi-disciplinary design optimisation #field programmable gate array
Tipo

Conference Paper