108 resultados para Socs


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Suppressors of cytokine signalling (SOCS, also known as CIS and SSI) are encoded by immediate early genes that act in a feedback loop to inhibit cytokine responses and activation of 'signal transducer and activator of transcription' (STAT). Here we show that SOCS-3 is strongly tyrosine-phosphorylated in response to many growth factors, including interleukin-2 (IL-2), erythropoietin (EPO), epidermal growth factor (EGF) and platelet-derived growth factor (PDGF). The principal phosphorylation sites on SOCS-3 are residues 204 and 221 at the carboxy terminus, and upon phosphorylation tyrosine 221 interacts with the Ras inhibitor p120 RasGAP. After IL-2 stimulation, phosphorylated SOCS-3 strongly inhibits STAT5 activation but, by binding to RasGAP, maintains activation of extracellular-signal-regulated kinase (ERK). A tyrosine mutant of SOCS-3 still blocks STAT phosphorylation, but also strongly inhibits IL-2-dependent activation of ERK and cell proliferation. Moreover, it also inhibits EPO- and PDGF-induced proliferation and ERK activation. Therefore, although SOCS proteins inhibit growth-factor responses, tyrosine phosphorylation of SOCS-3 can ensure cell survival and proliferation through the Ras pathway.

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Suppressors of cytokine signaling (SOCS) proteins are a family of proteins that are able to act in a classic negative feedback loop to regulate cytokine signal transduction. The regulation of the immune response by SOCS proteins may contribute to persistent infection or even a fatal outcome. In this study, we have investigated the induction of SOCS 1-3 after peripheral infection with West Nile virus (WNV) or tick-borne encephalitis virus (TBEV) in the murine model. We have shown that the cytokine response after infection of mice with WNV or TBEV induces an upregulation in the brain of mRNA transcripts for SOCS 1 and SOCS 3, but not SOCS 2. We hypothesize that SOCS proteins may play a role in limiting cytokine responses in the brain as a neuroprotective mechanism, which may actually enhance the ability of neuroinvasive viruses such as WNV and TBEV to spread and cause disease.

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Cytokines are important modulators of homeostatic processes such as development, haematopoiesis and host defence, A recently identified family of proteins, the supressors of cytokine signalling (SOCS) act as negative regulators of the key cytokine-activated signalling pathway, the Janus kinase/signal transducers and activators of transcription (JAK/STAT) cascade, In the current review, the discovery, structural features, regulation of expression, mechanisms of JAK/STAT inhibition and putative role in health and disease of the SOCS family are discussed.

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Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

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Power capping is a fundamental method for reducing the energy consumption of a wide range of modern computing environments, ranging from mobile embedded systems to datacentres. Unfortunately, maximising performance and system efficiency under static power caps remains challenging, while maximising performance under dynamic power caps has been largely unexplored. We present an adaptive power capping method that reduces the power consumption and maximizes the performance of heterogeneous SoCs for mobile and server platforms. Our technique combines power capping with coordinated DVFS, data partitioning and core allocations on a heterogeneous SoC with ARM processors and FPGA resources. We design our framework as a run-time system based on OpenMP and OpenCL to utilise the heterogeneous resources. We evaluate it through five data-parallel benchmarks on the Xilinx SoC which allows fully voltage and frequency control. Our experiments show a significant performance boost of 30% under dynamic power caps with concurrent execution on ARM and FPGA, compared to a naive separate approach.