Performance Analysis of MQAM-OFDM based WLAN in presence of Zigbee interference in AWGN and Rayleigh fading channel

In this paper we give the performance of MQAM OFDM based WLAN in presence of single and multiple channels Zigbee interference. An analytical model for getting symbol error rate (SER) in presence of single and multiple channel Zigbee interference in AWGN and Rayleigh fading channel for MQAM OFDM system is given. Simulation results are compared with analytical symbol error rate (SER) of the MQAM-OFDM system. For analysis we have modeled the Zigbee interference using the power spectral density (PSD) of OQPSK modulation and finding the average interference power for each sub-carrier of the OFDM system. Then we have averaged the SER over all WLAN sub-carriers. Simulations closely match with the analytical models. It is seen from simulation and analytical results that performance of WLAN is severely affected by Zigbee interference. Symbol error rate (SER) for 16QAM and 64QAM OFDM system is of order of 10(-2) for SIR (signal to interference ratio) of 20dB and 30dB respectively in presence of single Zigbee interferer inside the WLAN frequency band for Rayleigh fading channel. For SIR values more than 30dB and 40dB the SER approaches the SER without interference for 16QAM and 64QAM OFDM system respectively.

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.