Semi-insulating layer for novel high voltage polysilicon thin film transistors

This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region. A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10-7 Ω-1cm-1. Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.

Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

Silicon-on-insulating multi-layers for total-dose irradiation hardness

Silicon-on-insulating multi-layer (SOIM) materials were fabricated by co-implantation of oxygen and nitrogen ions with different energies and doses. The multilayer microstructure was investigated by cross-sectional transmission electron microscopy. P-channel metal-oxide-semiconductor (PMOS) transistors and metal-semiconductor-insulator-semiconductor (MSIS) capacitors were produced by these materials. After the irradiated total dose reaches 3 x 10(5) rad (Si), the threshold voltage of the SOIM-based PMOS transistor only shifts 0.07 V, while thin silicon-on-insulating buried-oxide SIMOX-based PMOS transistors have a shift of 1.2V, where SIMOX represents the separated by implanted oxygen. The difference of capacitance of the SOIM-based MSIS capacitors before and after irradiation is less than that of the thin-box SIMOX-based MSIS capacitor. The results suggest that the SOIM materials have a more remarkable irradiation tolerance of total dose effect, compared to the thin-buried-oxide SIMOX materials.

Formation of total-dose-radiation hardened materials by sequential oxygen and nitrogen implantation and multi-step annealing

Separation by implantation of oxygen and nitrogen (SIMON) silicon-on-insulator (SOI) materials were fabricated by sequential oxygen and nitrogen implantation with annealing after each implantation. Analyses of SIMS, XTEM and HRTEM were performed. The results show that superior buried insulating multi-layers were well formed and the possible mechanism is discussed. The remarkable total-dose irradiation tolerance of SIMON materials was confirmed by few shifts of drain leakage current-gate source voltage (I-V) curves of PMOS transistors fabricated on SIMON materials before and after irradiation.

Annealing and activation of silicon implanted in semi-insulating InP substrates

We have investigated the annealing and activation of silicon implanted in both as-grown Fe-doped semi-insulating (SI) InP substrate and undoped SI InP substrate obtained by annealing high purity conductive InP wafer (wafer-annealed). Si implantations were performed at an energy of 500 keV and a dose of 1 X 10(15) cm(-2). Following the implantations, rapid thermal annealing (RTA) cycles were carried out for 30 s at different temperatures. The results of Raman measurements show that for 700degreesC/30s RTA, the two Si-implanted SI InP substrates have acquired a high degree of lattice recovery and electrical activation. However, further Hall measurements indicate that the carrier concentration of the wafer-annealed SI InP substrate is about three times higher than that of the as-grown Fe-doped SI InP substrate. The difference can be ascribed to the low Fe concentration of the wafer-annealed SI InP substrate.These experimental data imply that the use of the wafer-annealed SI InP substrate can be conducive to the improvement of InP-based device performances. (C) 2003 Elsevier Ltd. All rights reserved.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Space grown semi-insulating gallium arsenide single crystal and its application

Low noise field effect transistors and analogue switch integrated circuits (ICs) have been fabricated in semi-insulating gallium arsenide (SI-GaAs) wafers grown in space by direct ion-implantation. The electrical behaviors of the devices and the ICs have surpassed those fabricated in the terrestrially grown SI-GaAs wafers. The highest gain and the lowest noise of the transistors made from space-grown SI-GaAs wafers are 22.8 dB and 0.78 dB, respectively. The threshold back-gating voltage of the ICs made from space-grown SI-GaAs wafers is better than 8.5 V The con-elation between the characterizations of materials and devices is studied systematically. (C) 2002 COSPAR. Published by Elsevier Science Ltd. All rights reserved.

Characterization of defects and whole wafer uniformity of annealed undoped semi-insulating InP wafers

Semi-insulating (SI) InP wafers of 2 and 3 in. diameters have been prepared by annealing undoped LEC InP at 930 degreesC for 80 h under pure phosphorus ambient (PP) and iron phosphide ambient (IP). The electrical uniformity of annealed undoped SI wafers, along with a Fe-doped as-grown SI LEC InP wafer, has been characterized by whole wafer PL mapping and radial Hall measurements. Defects in these wafers have been detected by photo-induced current transient spectroscopy (PICTS). The results indicated that the uniformity of IP wafer is much better than that of PP wafer and as-grown Fe-doped Si InP wafer. There are fewer traps in undoped SI InP IP wafer than in as grown Fe-doped and undoped SI InP PP wafer, as evidenced by PICTS. The good uniformity of the IP wafer is related to the nonexistence of high concentration of thermally induced defects. The mechanism for this phenomenon is discussed based on the results. (C) 2002 Elsevier Science B.V. All rights reserved.

Semi-insulating GaAs grown in outer space

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

Outer space grown semi-insulating GaAs and its applications

GaAs single crystal has been grown in recoverable satellite. Hall measurements indicate that the GaAs shows semi-insulating behavior. The structural properties of the crystal have been improved obviously, and their uniformity has been improved as well. The stoichiometry and its distribution in space-grown GaAs are improved greatly compared with the GaAs single crystal grown terrestrially. The properties of integrated circuits made by direct ion-implantation on space-grown GaAs are better than those made on ground-grown materials. These results show that the stoichiometry in semi-insulating GaAs seriously affects the properties of related devices.

Recent research results on deep level defects in semi-insulating InP - Application to improve material quality

An apparent defect suppression effect has been observed in InP through an investigation of deep level defects in different semi-insulating (SI) InP materials. Quality improvement of SI-InP based on the defect suppression mechanism is presented.

Improvement of the electrical property of semi-insulating InP by suppression of compensation defects

Semi-insulating (SI) InP obtained by iron phosphide ambient annealing has very low concentration of deep level defects and better electrical property than SI-InP annealed in phosphorus ambient. The defect suppression phenomenon correlates with Fe diffusion and substitution in the annealing process. Analysis of the experimental result suggests that a high activation ratio of incorporated Fe in InP has an effect of defect suppression in Fe-doped and Fe-diffused SI-InP.