An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

High mobility organic thin film transistor and efficient photovoltaic devices using versatile donor-acceptor polymer semiconductor by molecular design

In this work, we report a novel donor-acceptor based solution processable low band gap polymer semiconductor, PDPP-TNT, synthesized via Suzuki coupling using condensed diketopyrrolopyrrole (DPP) as an acceptor moiety with a fused naphthalene donor building block in the polymer backbone. This polymer exhibits p-channel charge transport characteristics when used as the active semiconductor in organic thin-film transistor (OTFT) devices. The hole mobilities of 0.65 cm2 V-1 s-1 and 0.98 cm2 V -1 s-1 are achieved respectively in bottom gate and dual gate OTFT devices with on/off ratios in the range of 105 to 10 7. Additionally, due to its appropriate HOMO (5.29 eV) energy level and optimum optical band gap (1.50 eV), PDPP-TNT is a promising candidate for organic photovoltaic (OPV) applications. When this polymer semiconductor is used as a donor and PC71BM as an acceptor in OPV devices, high power conversion efficiencies (PCE) of 4.7% are obtained. Such high mobility values in OTFTs and high PCE in OPV make PDPP-TNT a very promising polymer semiconductor for a wide range of applications in organic electronics.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold

The three-dimensional spatial distribution of Al in the high-k metal gates of metal-oxide-semiconductor field-effect-transistors is measured by atom probe tomography. Chemical distribution is correlated with the transistor voltage threshold (VTH) shift generated by the introduction of a metallic Al layer in the metal gate. After a 1050 °C annealing, it is shown that a 2-Å thick Al layer completely diffuses into oxide layers, while a positive VTH shift is measured. On the contrary, for thicker Al layers, Al precipitation in the metal gate stack is observed and the VTH shift becomes negative. © 2012 American Institute of Physics.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

Design of a high sensitive double-gate field-effect transistor biosensor for DNA detection

The study of interactions between organic biomolecules and semiconducting surfaces is an important consideration for the design and fabrication of field-effect-transistor (FET) biosensor. This paper demonstrates DNA detection by employing a double-gate field effect transistor (DGFET). In addition, an investigation of sensitivity and signal to noise ratio (SNR) is carried out for different values of analyte concentration, buffer ion concentration, pH, reaction constant, etc. Sensitivity, which is indicated by the change of drain current, increases non-linearly after a specific value (∼1nM) of analyte concentration and decreases non-linearly with buffer ion concentration. However, sensitivity is linearly related to the fluidic gate voltage. The drain current has a significant effect on the positive surface group (-NH2) compared to the negative counterpart (-OH). Furthermore, the sensor has the same response at a particular value of pH (5.76) irrespective of the density of surface group, although it decreases with pH value. The signal to noise ratio is improved with higher analyte concentrations and receptor densities.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Broken gates and leaky graves : spectral language and Australia's ghost stories

Ghost stories are unusual amongst supernatural literatures in their modelling of a recognisable, mimetic reality interrupted or infiltrated by immaterial forces. In its discussion of Australian ghost stories, this thesis advances a new approach to ghost narratives which seeks to model and articulate the mechanics of ghosts and hauntings as something reliant on and engaged with the material and the mundane.

A study of the effects metal residues in poly(9,9-dioctylfluorene) have on field-effect transistor device characteristics

The amount of metal residues from organometallic reagents used in preparation of poly(9,9-dioctylfluorene) by palladium catalysed Suzuki and nickel-induced Yamamoto polycondensations have been determined, and their effect upon the behaviour of the polymer in field-effect transistors (FETs) has been measured. The metal levels from material polymerised by Suzuki method were found to be much higher than from that made by the Yamamoto procedure. Simple treatment of the polymers with suitable metal trapping reagents lowered the metal levels significantly, with EDTA giving best results for nickel and triphenylphosphine for palladium. Comparison of the behaviour of FETs using polyfluorenes with varying levels of metal contamination, showed that the metal residues have little effect upon the mobility values, but often affect the degree of hysteresis, possibly acting as charge traps. Satisfactory device performances were obtained from polymer with palladium levels of 2000 μg/g suggesting that complete removal of metal residues may not be necessary for satisfactory device performance.

Synthesis, characterization and organic field effect transistor performance of a diketopyrrolopyrrole-fluorenone copolymer

A diketopyrrolopyrrole (DPP) with fluorenone (FN) based low band gap alternating copolymer (PDPPT-alt-FN) has been synthesized via Suzuki coupling. PDPPT-alt-FN exhibits a deep HOMO level with a lower band gap. Fabricated organic thin film transistors using PDPPT-alt-FN as a channel semiconductor show p-channel behaviour with the highest hole mobility of 0.083 cm2 V-1 s-1 measured in air.

Furan containing diketopyrrolopyrrole copolymers : synthesis, characterization, organic field effect transistor performance and photovoltaic properties

In this work, we report design, synthesis and characterization of solution processable low band gap polymer semiconductors, poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-phenylene} (PDPP-FPF), poly{3,6-difuran-2-yl-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1, 4-dione-alt-naphthalene} (PDPP-FNF) and poly{3,6-difuran-2-yl-2,5-di(2- octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione-alt-anthracene} (PDPP-FAF) using the furan-containing 3,6-di(furan-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione (DBF) building block. As DBF acts as an acceptor moiety, a series of donor-acceptor (D-A) copolymers can be generated when it is attached alternatively with phenylene, naphthalene or anthracene donor comonomer blocks. Optical and electrochemical characterization of thin films of these polymers reveals band gaps in the range of 1.55-1.64 eV. These polymers exhibit excellent hole mobility when used as the active layer in organic thin-film transistor (OTFT) devices. Among the series, the highest hole mobility of 0.11 cm 2 V -1 s -1 is achieved in bottom gate and top-contact OTFT devices using PDPP-FNF. When these polymers are used as a donor and [70]PCBM as the acceptor in organic photovoltaic (OPV) devices, power conversion efficiencies (PCE) of 2.5 and 2.6% are obtained for PDPP-FAF and PDPP-FNF polymers, respectively. Such mobility values in OTFTs and performance in OPV make furan-containing DBF a very promising block for designing new polymer semiconductors for a wide range of organic electronic applications.

Density of trap states in a polymer field-effect transistor

We report a more accurate method to determine the density of trap states in a polymer field-effect transistor. In the approach, we describe in this letter, we take into consideration the sub-threshold behavior in the calculation of the density of trap states. This is very important since the sub-threshold regime of operation extends to fairly large gate voltages in these disordered semiconductor based transistors. We employ the sub-threshold drift-limited mobility model (for sub-threshold response) and the conventional linear mobility model for above threshold response. The combined use of these two models allows us to extract the density of states from charge transport data much more accurately. We demonstrate our approach by analyzing data from diketopyrrolopyrrole based co-polymer transistors with high mobility. This approach will also work well for other disordered semiconductors in which sub-threshold conduction is important.

ACE research vignette 037 : Bill Gates’ mug shot : Is there a secret link between rule-breaking, crime, and entrepreneurship?

This series of research vignettes is aimed at sharing current and interesting research findings from international entrepreneurship researchers. In this vignette, Dr. Martin Obschonka, considers the relationship between entrepreneurship and rule-breaking.

Can the Gates Foundation be convinced to dump fossil fuels?

This week, The Guardian newspaper has campaigned for the Bill and Melinda Gates Foundation to divest its fossil fuel investments – which the newspaper claims are worth US$1.4 billion. The foundation can and should address the climate crisis, particularly given the threat it poses to food security, public health, human rights, and the development agenda.