High-performance FPGA implementation of DES using a novel method for implementing the key schedule

A generic, parameterisable key scheduling core is presented, which can be utilised in pipelinable private-key encryption algorithms. The data encryption standard (DES) algorithm, which lends itself readily to pipelining, is utilised to exemplify this novel key scheduling method and the broader applicability of the method to other encryption algorithms is illustrated. The DES design is implemented on Xilinx Virtex FPGA technology. Utilising the novel method, a 16-stage pipelined DES design is achieved, which can run at an encryption rate of 3.87 Gbit/s. This result is among the fastest hardware implementations and is a factor 28 times faster than software implementations.

Parameterizable QR core

The design of a generic QR core for adaptive beamforming is presented. The work relies on an existing mapping technique that can be applied to a triangular QR array in such a way to allow the generation of a range of QR architectures. All scheduling of data inputs and retiming to include processor latency has been included within the generic representation.

Improved Montgomery modular inverse algorithm

A new, single and unified Montgomery modular inverse algorithm, which performs both classical and Montgomery modular inversion, is proposed. This reduces the number of Montgomery multiplication operations required by 33% when compared with previous algorithms reported in the literature. The use of this in practice has been investigated by implementation of the improved unified algorithm and the previous algorithms on FPGA devices. The unified algorithm implementation shows a significant speed-up and a reduction in silicon area usage.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

Wavelet packet transforms for system-on-chip applications

A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.

An Integration Methodology for Automated Recurring Cost Prediction using Digital Manufacturing Technology

The need to account for the effect of design decisions on manufacture and the impact of manufacturing cost on the life cycle cost of any product are well established. In this context, digital design and manufacturing solutions have to be further developed to facilitate and automate the integration of cost as one of the major driver in the product life cycle management. This article is to present an integration methodology for implementing cost estimation capability within a digital manufacturing environment. A digital manufacturing structure of knowledge databases are set out and the ontology of assembly and part costing that is consistent with the structure is provided. Although the methodology is currently used for recurring cost prediction, it can be well applied to other functional developments, such as process planning. A prototype tool is developed to integrate both assembly time cost and parts manufacturing costs within the same digital environment. An industrial example is used to validate this approach.

Ultrafast low-loss 42-70 GHz differential SPDT switch in 0.35 μm SiGe technology

This paper presents an ultrafast wideband low-loss single-pole double-throw (SPDT) differential switch in 0.35 µ m SiGe bipolar technology. The proposed topology adopting current-steering technique results in a total measured switching time of 75 ps , which suggests a maximum switching rate of 13 Gb/s, the fastest ever reported at V-band. In addition, the switch exhibits an insertion loss lower than 1.25 dB and an isolation higher than 18 dB from 42 GHz to 70 GHz. © 2006 IEEE.

Amplitude-modulation characteristics of power-combining Class-E amplifier with finite choke

Power back-off performances of a new variant power-combining Class-E amplifier under different amplitude-modulation schemes such as continuous wave (CW), envelope elimination and restoration (EER), envelope tracking (ET) and outphasing are for the first time investigated in this study. Finite DC-feed inductances rather than massive RF chokes as used in the classic single-ended Class-E power amplifier (PA) resulted from the approximate yet effective frequency-domain circuit analysis provide the wherewithal to increase modulation bandwidth up to 80% higher than the classic single-ended Class-E PA. This increased modulation bandwidth is required for the linearity improvement in the EER/ET transmitters. The modified output load network of the power-combining Class-E amplifier adopting three-harmonic terminations technique relaxes the design specifications for the additional filtering block typically required at the output stage of the transmitter chain. Qualitative agreements between simulation and measurement results for all four schemes were achieved where the ET technique was proven superior to the other schemes. When the PA is used within the ET scheme, an increase of average drain efficiency of as high as 40% with respect to the CW excitation was obtained for a multi-carrier input signal with 12 dB peak-to-average power ratio. © 2011 The Institution of Engineering and Technology.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

W-Band Planar Wide-Angle Scanning Antenna Architecture

This paper proposes a hybrid scanning antenna architecture for applications in mm-wave intelligent mobile sensing and communications. We experimentally demonstrate suitable W-band leaky-wave antenna prototypes in substrate integrated waveguide (SIW) technology. Three SIW antennas have been designed that within a 6.5 % fractional bandwidth provide beam scanning over three adjacent angular sectors. Prototypes have been fabricated and their performance has been experimentally evaluated. The measured radiation patterns have shown three frequency scanning beams covering angles from 11 to 56 degrees with beamwidth of 10?±?3 degrees within the 88-94 GHz frequency range.

Illumination invariant facial recognition using a piecewise-constant lighting model

In this paper we demonstrate a simple and novel illumination model that can be used for illumination invariant facial recognition. This model requires no prior knowledge of the illumination conditions and can be used when there is only a single training image per-person. The proposed illumination model separates the effects of illumination over a small area of the face into two components; an additive component modelling the mean illumination and a multiplicative component, modelling the variance within the facial area. Illumination invariant facial recognition is performed in a piecewise manner, by splitting the face image into blocks, then normalizing the illumination within each block based on the new lighting model. The assumptions underlying this novel lighting model have been verified on the YaleB face database. We show that magnitude 2D Fourier features can be used as robust facial descriptors within the new lighting model. Using only a single training image per-person, our new method achieves high (in most cases 100%) identification accuracy on the YaleB, extended YaleB and CMU-PIE face databases.

Variable temperature electrochemical strain microscopy of Sm-doped ceria

Variable temperature electrochemical strain microscopy has been used to study the electrochemical activity of Sm-doped ceria as a function of temperature and bias. The electrochemical strain microscopy hysteresis loops have been collected across the surface at different temperatures and the relative activity at different temperatures has been compared. The relaxation behavior of the signal at different temperatures has been also evaluated to relate kinetic process during bias induced electrochemical reactions with temperature and two different kinetic regimes have been identified. The strongly non-monotonic dependence of relaxation behavior on temperature is interpreted as evidence for water-mediated mechanisms.

The partially reversible formation of Li-metal particles on a solid Li electrolyte:applications toward nanobatteries

The feasibility of large-scale implementation of Li-air batteries (LABs) hinges on understanding the thermodynamic and kinetic factors that control charge-discharge rates, efficiency and life times. Here, the kinetics of bias-induced reactions is explored locally on the surface of Li-ion conductive glass ceramics, a preferred electrolyte for LABs, using direct current-voltage and strain spectroscopies. Above a critical bias, particle growth kinetics were found to be linear in both the bias and time domains. Partial reversibility was observed for Li particles as evidenced by the presence of anodic peaks following the Li(+) reduction, as well an associated reduction in particle height. The degree of reversibility was highest for the smallest particles formed. These observations thus suggest the possibility of producing nanobatteries with an active anode volume of the order of 0.1 al.

XUV spectroscopic characterization of warm dense aluminum plasmas generated by the free-electron-laser FLASH

We report on experiments aimed at the generation and characterization of solid density plasmas at the free-electron laser FLASH in Hamburg. Aluminum samples were irradiated with XUV pulses at 13.5 nm wavelength (92 eV photon energy). The pulses with duration of a few tens of femtoseconds and pulse energy up to 100 mu J are focused to intensities ranging between 10(13) and 10(17) W/cm(2). We investigate the absorption and temporal evolution of the sample under irradiation by use of XUV and optical spectroscopy. We discuss the origin of saturable absorption, radiative decay, bremsstrahlung and atomic and ionic line emission. Our experimental results are in good agreement with simulations.