Highly linear low voltage low power CMOS LNA

A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching −1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Production grinding burn detection using acoustic emission and electric power signals

This work uses a monitoring system based on a PC platform, where the acoustic emission and electric power signals generated during the grinding process are used to investigate superficial burning occurrence in a surface grinding operation using two types of steel, three grinding conditions and an Al203 vitrified grinding wheel. Acoustic emission signals on the workpiece and grinding power were measured during a surface plunge operation until the grinding burn happened. From the results the standard deviation of the acoustic emission signal and the maximum electric power were calculated for each grinding pass. The proposed DPO parameter is the product between the power level and acoustic emission standard deviation. The results show that both signals can be used for burning detection, and the parameter DPO is the best indicator for the burning studied in this work. This can be explained by the high dispersion of the acoustic emission RMS level associated to the high power consumption when the grinding wheel lose its sharpness.

Consumer behavior after the Brazilian power rationing in 2001

In June 2001, after a dry period, the level of the water reservoirs in Brazil was below their operational levels. This situation, combined with other historical factors, led the country into a period of power rationing. As expected, power consumption lowered during this period. After December 2001, when the power rationing ended, electrical utilities expected to return to their normal power consumption in a matter of months, but the level of power consumption only returned to its level around years 2004 2005. Consumer behavior went through a change during this period, and the consumers kept this behavior after, leading to electrical and economical consequences until today. This paper presents an analysis of several factors that led to these events, including historical consumption data and comparisons with similar situations. The objective of this analysis is to give helpful information to electrical utilities, that could deal with similar situations, in their load forecasting studies. © 2006 IEEE.

Possible shunt compensation strategies based on conservative power theory

Considering the Conservative Power Theory (CPT), this paper proposes some novel compensation strategies for shunt passive or active devices. The CPT current decompositions result in several current terms, which are associated with specific physical phenomena (average power consumption P, energy storage Q, load and source distortion D, unbalances N). These current components were used in this work for the definition of different current compensators, which can be selective in terms of minimizing particular disturbing effects. Compensation strategies for single and three-phase four-wire circuits have also been considered. Simulation results have been demonstrated in order to validate the possibilities and performance of the proposed strategies. © 2010 IEEE.

Decoupled reference generator for shunt active filters using the conservative power theory

Based on the framework of the Conservative Power Theory (CPT), this paper proposes some compensation strategies for shunt current compensators. CPT current decompositions result in several current-related terms associated with specific load characteristics, such as power consumption, energy storage, unbalances and load nonlinearities. These current components are decoupled (orthogonal) from each other and are used here to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Compensation strategies for single- and three-phase four-wire circuits are also considered. Simulated and experimental results are described to validate the possibilities and performance of the proposed strategies. © 2013 Brazilian Society for Automatics - SBA.

Sistema de extração de potência (power harvesting) usando transdutores piezelétricos

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

NodePM: A Remote Monitoring Alert System for Energy Consumption Using Probabilistic Techniques

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Electric consumption in SHSs in rural communities of brazil and Peru and recommendations for sizing

The lack of data records of electric power consumption of smallphotovoltaic home systems, independently of the method used for sizing them, drives to consider the demand as a constant. However, the existing data reveal the variability of the consumption due to the influences of some social, cultural and psychosocial aspects of the human groups. This paper presents records of consumption data obtainedfrom several solar home systems (SHSs) in Brazil and Peru, and it discusses about the Gamma distribution function that can express to a great extent the behaviour of the demand. By this analysis it was verified that `a lot of people consume little and few people consume a lot`. In that sense, a few recommendations for sizing procedures that can be useful in the implantation of extensive programmes of rural electrification by SHSs are presented. Copyright (c) 2007 John Wiley & Sons, Ltd.

A Low Power CMOS Voltage Regulator for a Wireless Blood Pressure Biosensor

This paper describes a CMOS implementation of a linear voltage regulator (LVR) used to power up implanted physiological signal systems, as it is the case of a wireless blood pressure biosensor. The topology is based on a classical structure of a linear low-dropout regulator. The circuit is powered up from an RF link, thus characterizing a passive radio frequency identification (RFID) tag. The LVR was designed to meet important features such as low power consumption and small silicon area, without the need for any external discrete components. The low power operation represents an essential condition to avoid a high-energy RF link, thus minimizing the transmitted power and therefore minimizing the thermal effects on the patient's tissues. The project was implemented in a 0.35-mu m CMOS process, and the prototypes were tested to validate the overall performance. The LVR output is regulated at 1 V and supplies a maximum load current of 0.5 mA at 37 degrees C. The load regulation is 13 mV/mA, and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW.

Dynamic power management: from portable devices to high performance computing

Electronic applications are nowadays converging under the umbrella of the cloud computing vision. The future ecosystem of information and communication technology is going to integrate clouds of portable clients and embedded devices exchanging information, through the internet layer, with processing clusters of servers, data-centers and high performance computing systems. Even thus the whole society is waiting to embrace this revolution, there is a backside of the story. Portable devices require battery to work far from the power plugs and their storage capacity does not scale as the increasing power requirement does. At the other end processing clusters, such as data-centers and server farms, are build upon the integration of thousands multiprocessors. For each of them during the last decade the technology scaling has produced a dramatic increase in power density with significant spatial and temporal variability. This leads to power and temperature hot-spots, which may cause non-uniform ageing and accelerated chip failure. Nonetheless all the heat removed from the silicon translates in high cooling costs. Moreover trend in ICT carbon footprint shows that run-time power consumption of the all spectrum of devices accounts for a significant slice of entire world carbon emissions. This thesis work embrace the full ICT ecosystem and dynamic power consumption concerns by describing a set of new and promising system levels resource management techniques to reduce the power consumption and related issues for two corner cases: Mobile Devices and High Performance Computing.

Ultra-low power WSNs: distributed signal processing and dynamic resource management

This thesis presents several data processing and compression techniques capable of addressing the strict requirements of wireless sensor networks. After introducing a general overview of sensor networks, the energy problem is introduced, dividing the different energy reduction approaches according to the different subsystem they try to optimize. To manage the complexity brought by these techniques, a quick overview of the most common middlewares for WSNs is given, describing in detail SPINE2, a framework for data processing in the node environment. The focus is then shifted on the in-network aggregation techniques, used to reduce data sent by the network nodes trying to prolong the network lifetime as long as possible. Among the several techniques, the most promising approach is the Compressive Sensing (CS). To investigate this technique, a practical implementation of the algorithm is compared against a simpler aggregation scheme, deriving a mixed algorithm able to successfully reduce the power consumption. The analysis moves from compression implemented on single nodes to CS for signal ensembles, trying to exploit the correlations among sensors and nodes to improve compression and reconstruction quality. The two main techniques for signal ensembles, Distributed CS (DCS) and Kronecker CS (KCS), are introduced and compared against a common set of data gathered by real deployments. The best trade-off between reconstruction quality and power consumption is then investigated. The usage of CS is also addressed when the signal of interest is sampled at a Sub-Nyquist rate, evaluating the reconstruction performance. Finally the group sparsity CS (GS-CS) is compared to another well-known technique for reconstruction of signals from an highly sub-sampled version. These two frameworks are compared again against a real data-set and an insightful analysis of the trade-off between reconstruction quality and lifetime is given.

DESIGN AND IMPLEMENT DYNAMIC PROGRAMMING BASED DISCRETE POWER LEVEL SMART HOME SCHEDULING USING FPGA

With the development and capabilities of the Smart Home system, people today are entering an era in which household appliances are no longer just controlled by people, but also operated by a Smart System. This results in a more efficient, convenient, comfortable, and environmentally friendly living environment. A critical part of the Smart Home system is Home Automation, which means that there is a Micro-Controller Unit (MCU) to control all the household appliances and schedule their operating times. This reduces electricity bills by shifting amounts of power consumption from the on-peak hour consumption to the off-peak hour consumption, in terms of different “hour price”. In this paper, we propose an algorithm for scheduling multi-user power consumption and implement it on an FPGA board, using it as the MCU. This algorithm for discrete power level tasks scheduling is based on dynamic programming, which could find a scheduling solution close to the optimal one. We chose FPGA as our system’s controller because FPGA has low complexity, parallel processing capability, a large amount of I/O interface for further development and is programmable on both software and hardware. In conclusion, it costs little time running on FPGA board and the solution obtained is good enough for the consumers.

NodePM: A Remote Monitoring Alert System for Energy Consumption Using Probabilistic Techniques

In this paper, we propose an intelligent method, named the Novelty Detection Power Meter (NodePM), to detect novelties in electronic equipment monitored by a smart grid. Considering the entropy of each device monitored, which is calculated based on a Markov chain model, the proposed method identifies novelties through a machine learning algorithm. To this end, the NodePM is integrated into a platform for the remote monitoring of energy consumption, which consists of a wireless sensors network (WSN). It thus should be stressed that the experiments were conducted in real environments different from many related works, which are evaluated in simulated environments. In this sense, the results show that the NodePM reduces by 13.7% the power consumption of the equipment we monitored. In addition, the NodePM provides better efficiency to detect novelties when compared to an approach from the literature, surpassing it in different scenarios in all evaluations that were carried out.

A low power routing algorithm for localization in IEEE 802.15.4 networks

Many context-aware applications rely on the knowledge of the position of the user and the surrounding objects to provide advanced, personalized and real-time services. In wide-area deployments, a routing protocol is needed to collect the location information from distant nodes. In this paper, we propose a new source-initiated (on demand) routing protocol for location-aware applications in IEEE 802.15.4 wireless sensor networks. This protocol uses a low power MAC layer to maximize the lifetime of the network while maintaining the communication delay to a low value. Its performance is assessed through experimental tests that show a good trade-off between power consumption and time delay in the localization of a mobile device.