Set theoretic operations on polygons using the scan-grid approach

This paper describes an algorithm to compute the union, intersection and difference of two polygons using a scan-grid approach. Basically, in this method, the screen is divided into cells and the algorithm is applied to each cell in turn. The output from all the cells is integrated to yield a representation of the output polygon. In most cells, no computation is required and thus the algorithm is a fast one. The algorithm has been implemented for polygons but can be extended to polyhedra as well. The algorithm is shown to take O(N) time in the average case where N is the total number of edges of the two input polygons.

New approach to improved detection and tracking performance in track-while-scan radars. Part 1: Introduction and review

The paper presents a new approach to improve the detection and tracking performance of a track-while-scan (TWS) radar. The contribution consists of three parts. In Part 1 the scope of various papers in this field is reviewed. In Part 2, a new approach for integrating the detection and tracking functions is presented. It shows how a priori information from the TWS computer can be used to improve detection. A new multitarget tracking algorithm has also been developed. It is specifically oriented towards solving the combinatorial problems in multitarget tracking. In Part 3, analytical derivations are presented for quantitatively assessing, a priori, the performance of a track-while-scan radar system (true track initiation, false track initiation, true track continuation and false track deletion characteristics). Simulation results are also shown.

New approach to improved detection and tracking performance in track-while-scan radars. Part 3: Performance prediction, optimisation and testing

The paper presents, in three parts, a new approach to improve the detection and tracking performance of a track-while-scan radar. Part 1 presents a review of the current status of the subject. Part 2 details the new approach. It shows how a priori information provided by the tracker can be used to improve detection. It also presents a new multitarget tracking algorithm. In the present Part, analytical derivations are presented for assessing, a priori, the performance of the TWS radar system. True track initiation, false track initiation, true track continuation and false track deletion characteristics have been studied. It indicates how the various thresholds can be chosen by the designer to optimise performance. Simulation results are also presented.

New approach to improved detection and tracking performance in track-while-scan radars. Part 2: Detection, track nitiation and association

he paper presents, in three parts, a new approach to improve the detection and tracking performance of a track-while-scan (TWS) radar. Part 1 presents a review of current status. In this part, Part 2, it is shown how the detection can be improved by utilising information from tracker. A new multitarget tracking algorithm, capable of tracking manoeuvring targets in clutter, is then presented. The algorithm is specifically tailored so that the solution to the combinatorial problem presented in a companion paper can be applied. The implementation aspects are discussed and a multiprocessor architecture identified to realise the full potential of the algorithm. Part 3 presents analytical derivations for quantitative assessment of the performance of the TWS radar system. It also shows how the performance can be optimised.

Parallel polygon scan conversion algorithms: Performance evaluation on a shared bus architecture

In this paper, three parallel polygon scan conversion algorithms have been proposed, and their performance when executed on a shared bus architecture has been compared. It has been shown that the parallel algorithm that does not use edge coherence performs better than those that use edge coherence. Further, a multiprocessing architecture has been proposed to execute the parallel polygon scan conversion algorithms more efficiently than a single shared bus architecture.

Screening of new lines of cereal grains for inclusion in Near Infra Red Scan calibrations

The project will provide enough data for a reliable and robust NIRs. It will more fully develop the in vitro method to enable less costly assessment of grains in the future. It will also provide a reliable assessment for DE which is the most expensive component of pig feed.

A genome wide linkage scan for dizygotic twinning in 525 families of mothers of dizygotic twins

BACKGROUND: The tendency to conceive dizygotic (DZ) twins is a complex trait influenced by genetic and environmental factors. To search for new candidate loci for twinning, we conducted a genome-wide linkage scan in 525 families using microsatellite and single nucleotide polymorphism marker panels. METHODS AND RESULTS: Non-parametric linkage analyses, including 523 families containing a total of 1115 mothers of DZ twins (MODZT) from Australia and New Zealand (ANZ) and The Netherlands (NL), produced four linkage peaks above the threshold for suggestive linkage, including a highly suggestive peak at the extreme telomeric end of chromosome 6 with an exponential logarithm of odds \[(exp)LOD] score of 2.813 (P = 0.0002). Since the DZ twinning rate increases steeply with maternal age independent of genetic effects, we also investigated linkage including only families where at least one MODZT gave birth to her first set of twins before the age of 30. These analyses produced a maximum expLOD score of 2.718 (P = 0.0002), largely due to linkage signal from the ANZ cohort, however, ordered subset analyses indicated this result is most likely a chance finding in the combined dataset. Linkage analyses were also performed for two large DZ twinning families from the USA, one of which produced a peak on chromosome 2 in the region of two potential candidate genes. Sequencing of FSHR and FIGLA, along with INHBB in MODZTs from two large NL families with family specific linkage peaks directly over this gene, revealed a potentially functional variant in the 5' untranslated region of FSHR that segregated with the DZ twinning phenotype in the Utah family. CONCLUSION: Our data provide further evidence for complex inheritance of familial DZ twinning.

A genome-wide linkage scan provides evidence for both new and previously reported loci influencing common migraine

Latent class analysis was performed on migraine symptom data collected in a Dutch population sample (N = 12,210, 59% female) in order to obtain empirical groupings of individuals suffering from symptoms of migraine headache. Based on these heritable groupings (h(2) = 0.49, 95% CI: 0.41-0.57) individuals were classified as affected (migrainous headache) or unaffected. Genome-wide linkage analysis was performed using genotype data from 105 families with at least 2 affected siblings. In addition to this primary phenotype, linkage analyses were performed for the individual migraine symptoms. Significance levels, corrected for the analysis of multiple traits, were determined empirically via a novel simulation approach. Suggestive linkage for migrainous headache was found on chromosomes 1 (LOD = 1.63; pointwise P = 0.0031), 13 (LOD = 1.63; P = 0.0031), and 20 (LOD = 1.85; P = 0.0018). Interestingly, the chromosome 1 peak was located close to the ATP1A2 gene, associated with familial hemiplegic migraine type 2 (FHM2). Individual symptom analysis produced a LOD score of 1.97 (P = 0.0013) on chromosome 5 (photo/phonophobia), a LOD score of 2.13 (P = 0.0009) on chromosome 10 (moderate/severe pain intensity) and a near significant LOD score of 3.31 (P = 0.00005) on chromosome 13 (pulsating headache). These peaks were all located near regions previously reported in migraine linkage studies. Our results provide important replication and support for the presence of migraine susceptibility genes within these regions, and further support the utility of an LCA-based phenotyping approach and analysis of individual symptoms in migraine genetic research. Additionally, our novel "2-step" analysis and simulation approach provides a powerful means to investigate linkage to individual trait components.

On Minimization of Peak Power for Scan Circuit during Test

Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply, voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing

Enhanced Scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial Enhanced Scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS'89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

Detection and Evaluation of Impact damage in CFRP Laminates Using Ultrasound C-Scan and IR Thermography

Advanced composite structural components made up of Carbon Fibre Reinforced Polymers (CFRP) used in aerospace structures such as in Fuselage, Leading & Trailing edges of wing and tail, Flaps, Elevator, Rudder and entire wing structures encounter most critical type of damage induced by low velocity impact (<10 m/s) loads. Tool dropped during maintenance & service,and hailstone impacts on runways are common and unavoidable low-velocity impacts. These lowvelocity impacts induce defects such as delaminations, matrix cracking and debonding in the layered material, which are sub-surface in nature and are barely visible on the surface known as Barely Visible Impact Damage (BVID). These damages may grow under service load, leading to catastrophic failure of the structure. Hence detection, evaluation and characterization of these types of damage is of major concern in aerospace industries as the life of the component depends on the size and shape of the damage.In this paper, details of experimental investigations carried out and results obtained from a low-velocity impact of 30 Joules corresponding to the hailstone impact on the wing surface,simulated on the 6 mm CFRP laminates using instrumented drop-weight impact testing machine are presented. The Ultrasound C-scan and Infrared thermography imaging techniques were utilized extensively to detect, evaluate and characterize impact damage across the thickness of the laminates.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.