SOI strip waveguide microring resonator for homogeneous biosensing

We report the simulation and analytical results obtained for homogenous or bulk sensing of protein on Siliconon- insulator strip waveguide based microring resonator. The radii of the rings considered are 5 μm and 20 μm; the waveguide dimensions are 300 × 300 nm. A gap of (i) 200 nm and (ii) 300 nm exists between the ring and the bus waveguide. The biomaterial is uniformly distributed over a thickness which exceeds the evanescent field penetration depth of 150 nm. The sensitivities of the resonators are 32.5 nm/RIU and 17.5 nm/RIU (RIU - Refractive index unit) respectively.

Effect of FIB milling on MEMS SOI cantilevers

Stress induced by Focused Ion Beam (FIB) milling of cantilevers fabricated on silicon-on-insulator (SOI) wafer has been studied. Milling induces stress gradients ranging from -10MPa/μm to -120MPa/μm, depending on the location of cantilevers from the point of milling. Simulations were done to estimate the stress in the milled cantilevers.

Stress Engineering using Si3N4 for stiction free release of SOI beams

We report on the effect of thin silicon nitride (Si3N4) induced tensile stress on the structural release of 200nm thick SOI beam, in the surface micro-machining process. A thin (20nm / 100nm) LPCVD grown Si3N4 is shown to significantly enhance the yield of released beam in wet release technique. This is especially prominent with increase in beam length, where the beams have higher tendency for stiction. We attribute this yield enhancement to the nitride induced tensile stress, as verified by buckling tendency and resonance frequency data obtained from optical profilometry and laser doppler vibrometry.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

3D thermo-electro-mechanical simulations of gas sensors based on SOI membranes

3D thermo-electro-mechanical device simulations are presented of a novel fully CMOS-compatible MOSFET gas sensor operating in a SOI membrane. A comprehensive stress analysis of a Si-SiO2-based multilayer membrane has been performed to ensure a high degree of mechanical reliability at a high operating temperature (e.g. up to 400°C). Moreover, optimisation of the layout dimensions of the SOI membrane, in particular the aspect ratio between the membrane length and membrane thickness, has been carried out to find the best trade-off between minimal device power consumption and acceptable mechanical stress.

Design and coupled-effect simulations of CMOS micro gas-sensors built on SOI thin membranes

This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro-thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

Design and simulations of SOI CMOS micro-hotplate gas sensors

This paper describes a new generation of integrated solid-state gas-sensors embedded in SOI micro-hotplates. The micro-hotplates lie on a SOI membrane and consist of MOSFET heaters that elevate the operating temperature, through self-heating, of a gas sensitive material. These sensors are fully compatible with SOI CMOS or BiCMOS technologies, offer ultra-low power consumption (under 100 mW), high sensitivity, low noise, low unit cost, reproducibility and reliability through the use of on-chip integration. In addition, the new integrated sensors offer a nearly uniform temperature distribution over the active area at its operating temperatures at up to about 300-350°C. This makes SOI-based gas-sensing devices particularly attractive for use in handheld battery-operated gas monitors. This paper reports on the design of a chemo-resistive gas sensor and proposes for the first time an intelligent SOI membrane microcalorimeter using active micro-FET heaters and temperature sensors. A comprehensive set of numerical and analogue simulations is also presented including complex 2D and 3D electro-thermal numerical analyses. © 2001 Elsevier Science B.V. All rights reserved.

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

Low loss HF band SOI wine glass bulk mode capacitive square-plate resonator

This paper reports on the design and electrical characterization of a single crystal silicon micromechanical square-plate resonator. The microresonator has been excited in the anti-symmetrical wine glass mode at a resonant frequency of 5.166 MHz and exhibits an impressive quality factor (Q) of 3.7 × 106 at a pressure of 33 mtorr. The device has been fabricated in a commercial foundry process. An associated motional resistance of approximately 50 kΩ using a dc bias voltage of 60 V is measured for a transduction gap of 2 νm due to the ultra-high Q of the resonator. This result corresponds to a frequency-Q product of 1.9 × 1013, the highest reported for a fundamental mode single-crystal silicon resonator and on par with some of the best quartz crystal resonators. The results are indicative of the superior performance of silicon as a mechanical material, and show that the wine glass resonant mode is beneficial for achieving high quality factors allowed by the material limit. © 2009 IOP Publishing Ltd.

Study of lateral mode SOI-MEMS resonators for reduced anchor loss

MEMS resonators fabricated in silicon-on-insulator (SOI) technology must be clamped to the substrate via anchoring stems connected either from within the resonator or through the sides, with the side-clamped solution often employed due to manufacturing constraints. This paper examines the effect of two types of commonly used side-clamped, anchoring-stem geometries on the quality factor of three different laterally-driven resonator topologies. This study employs an analytical framework which considers the relative distribution of strain energies between the resonating body and clamping stems. The ratios of the strain energies are computed using ANSYS FEA and used to provide an indicator of the expected anchor-limited quality factors. Three MEMS resonator topologies have been fabricated and characterized in moderate vacuum. The associated measured quality factors are compared against the computed strain energy ratios, and the trends are shown to agree well with the experimental data. © 2011 IOP Publishing Ltd.