Influence of Temperature and High Electric Field on Power Consumption by Piezoelectric Actuated Integrated Structure

The influence of electric field and temperature on power consumption of piezoelectric actuated integrated structure is studied by using a single degree of freedom mass-spring-damper system model coupled with a piezoactuator. The material lead zirconate titanate, is considered as it is capable of producing relatively high strains (e.g., 3000 mu epsilon). Actuators are often subject to high electric fields to increase the induced strain produced, resulting in field dependant piezoelectric coefficient d(31), dielectric coefficient epsilon(33) and dissipation factor delta. Piezostructures are also likely to be used across a wide range of temperatures in aerospace and undersea operations. Again, the piezoelectric properties can vary with temperature. Recent experimental studies by physics researchers have looked at the effect of high electric field and temperature on piezoelectric properties. These properties are used together with an impedance based power consumption model. Results show that including the nonlinear variation of dielectric permittivity and dissipation factor with electric field is important. Temperature dependence of the dielectric constant also should be considered.

Minimum power consumption for drag reduction on a circular cylinder by tangential surface motion

We investigate the effect of a prescribed tangential velocity on the drag force on a circular cylinder in a spanwise uniform cross flow. Using a combination of theoretical and numerical techniques we make an attempt at determining the optimal tangential velocity profiles which will reduce the drag force acting on the cylindrical body while minimizing the net power consumption characterized through a non-dimensional power loss coefficient (C-PL). A striking conclusion of our analysis is that the tangential velocity associated with the potential flow, which completely suppresses the drag force, is not optimal for both small and large, but finite Reynolds number. When inertial effects are negligible (R e << 1), theoretical analysis based on two-dimensional Oseen equations gives us the optimal tangential velocity profile which leads to energetically efficient drag reduction. Furthermore, in the limit of zero Reynolds number (Re -> 0), minimum power loss is achieved for a tangential velocity profile corresponding to a shear-free perfect slip boundary. At finite Re, results from numerical simulations indicate that perfect slip is not optimum and a further reduction in drag can be achieved for reduced power consumption. A gradual increase in the strength of a tangential velocity which involves only the first reflectionally symmetric mode leads to a monotonic reduction in drag and eventual thrust production. Simulations reveal the existence of an optimal strength for which the power consumption attains a minima. At a Reynolds number of 100, minimum value of the power loss coefficient (C-PL = 0.37) is obtained when the maximum in tangential surface velocity is about one and a half times the free stream uniform velocity corresponding to a percentage drag reduction of approximately 77 %; C-PL = 0.42 and 0.50 for perfect slip and potential flow cases, respectively. Our results suggest that potential flow tangential velocity enables energetically efficient propulsion at all Reynolds numbers but optimal drag reduction only for Re -> infinity. The two-dimensional strategy of reducing drag while minimizing net power consumption is shown to be effective in three dimensions via numerical simulation of flow past an infinite circular cylinder at a Reynolds number of 300. Finally a strategy of reducing drag, suitable for practical implementation and amenable to experimental testing, through piecewise constant tangential velocities distributed along the cylinder periphery is proposed and analysed.

Biodiesel Exhaust Treatment with HFAC Plasma supported by Red Mud: Study on DeNOx and power consumption

The concentration of Nitrogen Oxides (NOx) in engines which use biodiesel as fuel is higher compared to conventional diesel engine exhaust. In this paper, an attempt has been made to treat this exhaust using a combination of High frequency AC (HFAC) plasma and an industrial waste, Red Mud which shows proclivity towards Nitrogen dioxide (NO2) adsorption. The high frequency AC source in combination with the proposed compact double dielectric plasma reactors is relatively more efficient in converting Nitric Oxide (NO) to NO2. It has been shown that the plasma treated gas enhances the activity of red mud as an adsorbent/catalyst and about 60-72% NOx removal efficiency was observed at a specific energy of 250 J/L. The advantage in this method is the cost effectiveness and abundant availability of the waste red mud in the industry. Further, power estimation studies were carried out using Manley's equation for the two reactors employed in the experiment and a close agreement between experimental and predicted powers was observed. (C) 2015 The Authors. Published by Elsevier Ltd.

Low power pipelined TCAM employing mismatch dependent power allocation technique

This paper presents design of a Low power 256x72 bit TCAM in 0.13um CMOS technology. In contrast to conventional Match line (ML) sensing scheme in which equal power is consumed irrespective of match or mismatch, the ML scheme employed in this design allocates less power to match decisions involving a large number of mismatched bits. Typically, the probability of mismatch is high so this scheme results in significant CAM power reduction. We propose to use this technique along with pipelining of search operation in which the MLs are broken into several segments. Since most words fail to match in first segment, the search operation for subsequent segments is discontinued, resulting in further reduction in power consumption. The above architecture provides 70% power reduction while performing search in 3ns.

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

A Low Power Frequency Multiplication Technique for Zigbee Transceiver

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405-2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LC-VCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-mum RF process with spiral on-chip inductors and MIM (metal-insulator-metal) capacitor option.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Dual-Stage Power Management Algorithms for Energy Harvesting Sensors

In this paper, we propose power management algorithms for maximizing the utility of energy harvesting sensors (EHS) that operate purely on the basis of energy harvested from the environment. In particular, we consider communication (i.e., transmission and reception) power management issues for EHS under an energy neutrality constraint. We also consider the fixed power loss effects of the circuitry, the battery inefficiency and its storage capacity, in the design of the algorithms. We propose a two-stage structure that exploits the inherent difference in the timescales at which the energy harvesting and channel fading processes evolve, without loss of optimality of the resulting solution. The outer stage schedules the power that can be used by an inner stage algorithm, so as to maximize the long term average utility and at the same time maintain energy neutrality. The inner stage optimizes the communication parameters to achieve maximum utility in the short-term, subject to the power constraint imposed by the outer stage. We optimize the algorithms for different transmission schemes such as the truncated channel inversion and retransmission strategies. The performance of the algorithms is illustrated via simulations using solar irradiance data, and for the case of Rayleigh fading channels. The results demonstrate the significant performance benefits that can be obtained using the proposed power management algorithms compared to the energy efficient (optimum when there is no storage) and the uniform power consumption (optimum when the battery has infinite capacity and is perfectly efficient) approaches.

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).

Applying Genetic Algorithms to Optimize Power in Tiled SNUCA Chip Multicore Architectures

We propose a novel technique for reducing the power consumed by the on-chip cache in SNUCA chip multicore platform. This is achieved by what we call a "remap table", which maps accesses to the cache banks that are as close as possible to the cores, on which the processes are scheduled. With this technique, instead of using all the available cache, we use a portion of the cache and allocate lesser cache to the application. We formulate the problem as an energy-delay (ED) minimization problem and solve it offline using a scalable genetic algorithm approach. Our experiments show up to 40% of savings in the memory sub-system power consumption and 47% savings in energy-delay product (ED).