Thermo-optic variable optical attenuator with low power consumption fabricated on silicon-on-insulator by anisotropic chemical etching

A thermo-optic Mach-Zehnder (MZ) variable optical attenuator based on silicon waveguides with a large cross section was designed and fabricated on silicon-on-insulator (SOI) wafer. Multimode interferometers were used as power splitters and combiners in the MZ structure. In order to achieve a smooth interface, anisotropic chemical etching of silicon was used to fabricate the waveguides. Isolating grooves were introduced to reduce power consumption and device length. The device has a low power consumption of 210 mW and a response time of 50 mus. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

Low power-consumption and high response frequency thermo-optic variable optical Attenuators based on silicon-on-insulator materials

A novel silicon-on-insulator thermo-optic variable optical attenuator with isolated grooves based on a multimode interference coupler principle is fabricated by the inductive coupled plasma etching technology. The maximum fibre-to-fibre insertion loss is lower than 2.2 dB, the dynamic attenuation range is from 0 to 30 dB in the wavelength range 1500-1600 nm, and the maximum power consumption is only 140 mW. The response frequency of the fabricated variable optical attenuator is about 30 kHz. Compared to the variable optical attenuator without isolated grooves, the maximum power consumption decreases more than 220 mW, and the response frequency rises are more than 20 kHz.

Fabrication and analysis of 2x2 thermo-optic SOI waveguide switch with low power consumption and fast response by anisotropy chemical etching

A low power consumption 2 x 2 thermo-optic switch with fast response was fabricated on silicon-on-insulator by anisotropy chemical etching. Blocking trenches were etched on both sides of the phase-shifting arms to shorten device length and reduce power consumption. Thin top cladding layer was grown to reduce power consumption and switching time. The device showed good characteristics, including a low switching power of 145 mW and a fast switching speed of 8 +/- 1 mus, respectively. Two-dimensional finite element method was applied to simulate temperature field in the phase-shifting arm instead of conventional one-dimensional method. According to the simulated result, a new two-dimensional index distribution of phase-shifting arm was determined. Consequently finite-difference beam propagation method was employed to simulate the light propagation in the switch, and calculate the power consumption as well as the switching speed. The experimental results were in good agreement with the theoretical estimations. (C) 2004 Elsevier B.V. All rights reserved.

A low power consumption thermo-optic variable optical attenuator based on SOI material

A SOI thenno-optic variable optical attenuator with U-grooves based on a multimode interference coupler principle is fabricated. The dynamic attenuation range is 0 to 29 dB; at the wavelength range between 1510 nm and 1610nm, and the maximum power consumption is only l30mW. Compared to the variable optical attenuator without U-groove, the maximum power consumption decreases more than 230mW

Study on sensing properties of tin oxide CO gas sensor with low power consumption

In this paper, the fabrication method of a new type of carbon monoxide gas sensor based on SnOx with low power consumption and its sensing characteristics have been reported. The electric conductance of this type of sensor evolves oscillation form regularly when the sensor is exposed to low level of CO gas. The oscillation amplitude is directly proportional to the concentration of CO gas over a wide range. The effects of relevant factors. such as. humidity, temperature and interference gases on the sensor properties were examined. The sensing oscillation response mechanism was also discussed.

Low power 2 x 2 thermo-optic SOI waveguide switch fabricated by anisotropy chemical etching

A 2 x 2 thermo-optic (TO) Mach-Zehnder (MZ) switch based on silicon waveguides with large cross section was designed and fabricated on silicon-on-insulator (SOI) wafer. The multi-mode interferometers (MMI) were used as power splitter and combiner in MZ structure. In order to get smooth interface, anisotropy chemical wet-etching of silicon was used to fabricate the waveguides instead of dry-etching. Additional grooves were introduced to reduce power consumption. The device has a low switching power of 235 mW and a switching speed of 60 mus. (C) 2004 Elsevier B.V. All rights reserved.

SOC dynamic power management using artificial neural network

Dynamic Power Management (DPM) is a technique to reduce power consumption of electronic system by selectively shutting down idle components. In this article we try to introduce back propagation network and radial basis network into the research of the system-level power management policies. We proposed two PM policies-Back propagation Power Management (BPPM) and Radial Basis Function Power Management (RBFPM) which are based on Artificial Neural Networks (ANN). Our experiments show that the two power management policies greatly lowered the system-level power consumption and have higher performance than traditional Power Management(PM) techniques-BPPM is 1.09-competitive and RBFPM is 1.08-competitive vs. 1.79, 1.45, 1.18-competitive separately for traditional timeout PM, adaptive predictive PM and stochastic PM.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

Dynamic power management approaches based on neural network

Dynamic Power Management (DPM) is a technique to reduce power consumption of electronic system. by selectively shutting down idle components. In this article we try to introduce back propagation network and radial basis network into the research of the system-level policies. We proposed two PAY policies-Back propagation Power Management (BPPM) and Radial Basis Function Power management (RBFPM) which are based on Artificial Neural Networks (ANN). Our experiments show that the two power management policies greatly lowered the system-level power consumption and have higher performance than traditional Power Management(PM) techniques-BPPM is 1.09-competitive and RBFPM is 1.08-competitive vs. 1.79,145,1.18-competitive separately for traditional timeout PM, adaptive predictive PM and stochastic PM.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

SOC dynamic power management using artificial neural network

Dynamic Power Management (DPM) is a technique to reduce power consumption of electronic system by selectively shutting down idle components. In this article we try to introduce back propagation network and radial basis network into the research of the system-level power management policies. We proposed two PM policies-Back propagation Power Management (BPPM) and Radial Basis Function Power Management (RBFPM) which are based on Artificial Neural Networks (ANN). Our experiments show that the two power management policies greatly lowered the system-level power consumption and have higher performance than traditional Power Management(PM) techniques-BPPM is 1.09-competitive and RBFPM is 1.08-competitive vs. 1.79 . 1.45 . 1.18-competitive separately for traditional timeout PM . adaptive predictive PM and stochastic PM.

A power-saving scheme for IEEE 802.11 Ad hoc networks

In the Wireless Local Area Networks (WLANs), the terminals are often powered by battery, so the power-saving performance of the wireless network card is a very important issue. For IEEE 802.11 Ad hoc networks, a power-saving scheme is presented in Medium Access Control (MAC) layer to reduce the power consumption by allowing the nodes enter into the sleep mode, but the scheme is based on Time-Drive Scheme (TDS) whose power-saving efficiency becomes lower and lower with the network load increasing. This paper presented a novel energy-saving mechanism, called as Hybrid-Drive Scheme (HDS), which introduces into a Message.-Drive Scheme (MDS) and combines MDS with the conventional TDS. The MDS, could obtain high efficiency when the load is heavy; meanwhile the TDS has high efficiency when the network load is small. The analysis shows that the proposed HDS could obtain high energy-efficiency whether the network load is light or heavy and have higher energy-saving efficiency than conventional scheme in the IEEE 802.11 standard.