Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization

This paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.

CSR数字高频分析系统的同步采样器HDL设计

本文主要阐述了CSR数字高频分析系统的同步采样器的研究、设计和实现，该分析系统是基于软件无线电技术构建的。 本文的创新点主要在于提出了一种很好的正交同步欠采样方法，这种基于软件无线电原理的I、Q两路正交同步的采样方法，主要利用了平方律部件、一阶环路滤波器和NCO来对I、Q两路采样触发脉冲上升沿的时间差进行闭环控制，从而实现对高频信号的数据采集和处理。这种方法降低了对AD芯片采样速率要求，同时也为后续的基带信号处理提供了方便。 在整个同步采样系统的实现过程中我采用了功能强大的Matlab7.0作为通信算法的仿真平台，选用了AD6645、StratixIIEP2S60和DSP6416作为主要的硬件平台，并在SynaptiCAD和ModelSim中做出了FPGA的HDL程序设计及波形实现