Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

10-Gbit/s transmission over 300-m standard multimode fiber using multilevel coding and 2-channel WDM

A combination of multilevel coding schemes and simple two-channel wavelength division multiplexing (WDM) at 1300 and 1550 nm was used to transmit an aggregate of 10 Gbit/s over 300 m of multimode fiber that is typical of that employed in current Local Area Networks (LANs). It was shown that this technique could be a simple solution for achieving 10 Gigabit ethernet links over installed multimode fiber building backbones.