A petri net based timing model for hardware/software co-design of digital systems
| Contribuinte(s) |
Universidade Estadual Paulista (UNESP) |
|---|---|
| Data(s) |
27/05/2014
27/05/2014
01/12/2004
|
| Resumo |
We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE. |
| Formato |
65-68 |
| Identificador |
http://dx.doi.org/10.1109/APCCAS.2004.1412692 IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, v. 1, p. 65-68. http://hdl.handle.net/11449/67969 10.1109/APCCAS.2004.1412692 WOS:000227668700017 2-s2.0-13444251353 |
| Idioma(s) |
eng |
| Relação |
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS |
| Direitos |
closedAccess |
| Palavras-Chave | #Computational complexity #Computer hardware #Computer science #Computer software #Embedded systems #Field programmable gate arrays #Mathematical models #Timing devices #Cooperative design (co-design) #Digital systems #Merlin's time model #Networks on chip (NoC) #Petri nets |
| Tipo |
info:eu-repo/semantics/conferencePaper |
