TLM2.0 based timing accurate modeling method for complex NoC systems
Data(s) |
2010
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Resumo |
Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE. |
Identificador | |
Idioma(s) |
eng |
Publicador |
Institute of Electrical and Electronics Engineers (IEEE) |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
Lu , Y , Sezer , S & McCanny , J 2010 , TLM2.0 based timing accurate modeling method for complex NoC systems . in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS) . Institute of Electrical and Electronics Engineers (IEEE) , pp. 2900-2903 , IEEE International Symposium on Circuits and Systems (ISCAS) , Paris , France , 1-1 May . DOI: 10.1109/ISCAS.2010.5538041 |
Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700/1708 #Hardware and Architecture #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
Tipo |
contributionToPeriodical |