Linear QR architecture for a single chip adaptive beamformer
Data(s) |
2000
|
---|---|
Resumo |
This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs. |
Identificador |
http://www.scopus.com/inward/record.url?scp=0033885979&partnerID=8YFLogxK |
Idioma(s) |
eng |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
Lightbody , G , Walke , R , Woods , R & McCanny , J 2000 , ' Linear QR architecture for a single chip adaptive beamformer ' Journal of VLSI signal processing systems for signal, image and video technology , vol 24 , no. 1 , pp. 67-81 . |
Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700/1710 #Information Systems #/dk/atira/pure/subjectarea/asjc/1700/1711 #Signal Processing #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
Tipo |
article |