JFET SOS devices: Processing and gamma radiation effects

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

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Chinese Inst Electr.; IEEE Electron Devices Soc.; IEEE Solid State Circuits Soc.; Japan Soc Appl Phys.; URSI Commiss D.; IEE, Electr Div, UK.; Korea Inst Telemat & Electr.; IEEE Beijing Sect.; Mat Res Soc.; Natl Nat Sci Fdn China.

Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China

Chinese Inst Electr.; IEEE Electron Devices Soc.; IEEE Solid State Circuits Soc.; Japan Soc Appl Phys.; URSI Commiss D.; IEE, Electr Div, UK.; Korea Inst Telemat & Electr.; IEEE Beijing Sect.; Mat Res Soc.; Natl Nat Sci Fdn China.