Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

zhangdi于2010-03-09批量导入

zhangdi于2010-03-09批量导入

IEEE Beijing Sect.; Chinese Inst Elect.; IEEE Electron Devices Soc.; IEEE EDS Beijing Chapter.; IEEE Solid State Circuits Soc.; IEEE Circuites & Syst Soc.; IEEE Hong Kong EDS, SSCS Chapter.; IEEE SSCS Beijing Chapter.; Japan Soc Appl Phys.; Elect Div IEEE.; URSI Commiss D.; Inst Elect Engineers Korea.; Assoc Asia Pacific Phys Soc.; Peking Univ, IEEE EDS Student Chapter.

[Yang, Zhichao; Chen, Stanley L.; Liu, Zhongli] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China

IEEE Beijing Sect.; Chinese Inst Elect.; IEEE Electron Devices Soc.; IEEE EDS Beijing Chapter.; IEEE Solid State Circuits Soc.; IEEE Circuites & Syst Soc.; IEEE Hong Kong EDS, SSCS Chapter.; IEEE SSCS Beijing Chapter.; Japan Soc Appl Phys.; Elect Div IEEE.; URSI Commiss D.; Inst Elect Engineers Korea.; Assoc Asia Pacific Phys Soc.; Peking Univ, IEEE EDS Student Chapter.